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-rw-r--r--include/llvm/Target/TargetInstrInfo.h43
-rw-r--r--lib/CodeGen/MachineInstr.cpp4
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp8
-rw-r--r--lib/CodeGen/TargetInstrInfoImpl.cpp2
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp8
-rw-r--r--utils/TableGen/InstrInfoEmitter.cpp6
6 files changed, 42 insertions, 29 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index cb67d713b2..bec3ba640c 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -32,14 +32,14 @@ class SelectionDAG;
template<class T> class SmallVectorImpl;
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
// Data types used to define information about a single machine instruction
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
typedef short MachineOpCode;
typedef unsigned InstrSchedClass;
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
@@ -124,24 +124,25 @@ const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
// both! If neither flag is set, then the instruction *always* has side effects.
const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
+
+//===----------------------------------------------------------------------===//
// Machine operand flags
-// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
-// requires a callback to look up its register class.
-const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
-
-/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
-/// predicate operand that controls an M_PREDICATED instruction.
-const unsigned M_PREDICATE_OPERAND = 1 << 1;
-
-/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
-///
-const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
-
+//===----------------------------------------------------------------------===//
+
namespace TOI {
// Operand constraints: only "tied_to" for now.
enum OperandConstraint {
TIED_TO = 0 // Must be allocated the same register as.
};
+
+ /// OperandFlags - These are flags set on operands, but should be considered
+ /// private, all access should go through the TargetOperandInfo accessors.
+ /// See the accessors for a description of what these are.
+ enum OperandFlags {
+ LookupPtrRegClass = 1 << 0,
+ Predicate = 1 << 1,
+ OptionalDef = 1 << 2
+ };
}
/// TargetOperandInfo - This holds information about one operand of a machine
@@ -157,6 +158,18 @@ public:
/// bits are used to specify the value of constraints (4 bits each).
unsigned int Constraints;
/// Currently no other information.
+
+ /// isLookupPtrRegClass - Set if this operand is a pointer value and it
+ /// requires a callback to look up its register class.
+ bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
+
+ /// isPredicate - Set if this is one of the operands that made up of
+ /// the predicate operand that controls an M_PREDICATED instruction.
+ bool isPredicate() const { return Flags & TOI::Predicate; }
+
+ /// isOptionalDef - Set if this operand is a optional def.
+ ///
+ bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
};
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 40ab4c2dd9..49b7ef2682 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -541,7 +541,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
const TargetInstrDescriptor *TID = getDesc();
if (TID->isPredicable()) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+ if (TID->OpInfo[i].isPredicate())
return i;
}
@@ -591,7 +591,7 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) {
const TargetInstrDescriptor *TID = MI->getDesc();
if (TID->isPredicable()) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+ if (TID->OpInfo[i].isPredicate()) {
// Predicated operands must be last operands.
addOperand(MI->getOperand(i));
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3ef907ee1a..e3e54c50a9 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -296,9 +296,9 @@ static const TargetRegisterClass *getInstrOperandRegClass(
assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
return NULL;
}
- const TargetOperandInfo &toi = II->OpInfo[Op];
- return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
- ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+ if (II->OpInfo[Op].isLookupPtrRegClass())
+ return TII->getPointerRegClass();
+ return MRI->getRegClass(II->OpInfo[Op].RegClass);
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
@@ -435,7 +435,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned VReg = getVR(Op, VRBaseMap);
const TargetInstrDescriptor *TID = MI->getDesc();
bool isOptDef = (IIOpNum < TID->numOperands)
- ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
+ ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 207f371b09..4498c984e2 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -38,7 +38,7 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
const TargetInstrDescriptor *TID = MI->getDesc();
if (TID->isPredicable()) {
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+ if (TID->OpInfo[i].isPredicate()) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg()) {
MO.setReg(Pred[j].getReg());
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index ea49b42c37..d79c1edf9f 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1882,7 +1882,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
const TargetInstrDescriptor &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
- const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
SmallVector<MachineOperand,4> AddrOps;
SmallVector<MachineOperand,2> BeforeOps;
@@ -1957,7 +1957,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
// Emit the store instruction.
if (UnfoldStore) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
- const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
}
@@ -1981,7 +1981,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
bool FoldedStore = I->second.second & (1 << 5);
const TargetInstrDescriptor &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
- const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
std::vector<SDOperand> AddrOps;
std::vector<SDOperand> BeforeOps;
@@ -2013,7 +2013,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
const TargetRegisterClass *DstRC = 0;
if (TID.numDefs > 0) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
- DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ DstRC = DstTOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
VTs.push_back(*DstRC->vt_begin());
}
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 93642f904b..6d08b20f3a 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -94,17 +94,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
// Ptr value whose register class is resolved via callback.
if (OpR->getName() == "ptr_rc")
- Res += "|M_LOOK_UP_PTR_REG_CLASS";
+ Res += "|TOI::LookupPtrRegClass";
// Predicate operands. Check to see if the original unexpanded operand
// was of type PredicateOperand.
if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
- Res += "|M_PREDICATE_OPERAND";
+ Res += "|TOI::Predicate";
// Optional def operands. Check to see if the original unexpanded operand
// was of type OptionalDefOperand.
if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
- Res += "|M_OPTIONAL_DEF_OPERAND";
+ Res += "|TOI::OptionalDef";
// Fill in constraint info.
Res += ", " + Inst.OperandList[i].Constraints[j];
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 00:44:45 +0000