diff options
| -rw-r--r-- | include/llvm/CodeGen/LiveVariables.h | 6 | ||||
| -rw-r--r-- | lib/CodeGen/LiveVariables.cpp | 49 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/x86-64-ret0.ll | 8 |
4 files changed, 63 insertions, 6 deletions
diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h index aa3b765a83..977b87a4be 100644 --- a/include/llvm/CodeGen/LiveVariables.h +++ b/include/llvm/CodeGen/LiveVariables.h @@ -165,6 +165,12 @@ private: // Intermediate data structures void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); void HandlePhysRegDef(unsigned Reg, MachineInstr *MI); + /// hasRegisterUseBelow - Return true if the specified register is used after + /// the current instruction and before it's next definition. + bool hasRegisterUseBelow(unsigned Reg, + MachineBasicBlock::iterator I, + MachineBasicBlock *MBB); + /// analyzePHINodes - Gather information about the PHI nodes in here. In /// particular, we want to map the variable information of a virtual /// register which is used in a PHI node. We map that to the BB the vreg diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 27f459d4f9..35461ef7db 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -267,8 +267,9 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI, if (*SubRegs == 0) { // No sub-registers, just check if reg is killed by RefMI. - if (PhysRegInfo[Reg] == RefMI) + if (PhysRegInfo[Reg] == RefMI && PhysRegInfo[Reg]->readsRegister(Reg)) { return true; + } } else if (SubKills.empty()) { // None of the sub-registers are killed elsewhere. return true; @@ -297,6 +298,34 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) { return false; } +/// hasRegisterUseBelow - Return true if the specified register is used after +/// the current instruction and before it's next definition. +bool LiveVariables::hasRegisterUseBelow(unsigned Reg, + MachineBasicBlock::iterator I, + MachineBasicBlock *MBB) { + if (I == MBB->end()) + return false; + ++I; + // FIXME: This is slow. We probably need a smarter solution. Possibilities: + // 1. Scan all instructions once and build def / use information of physical + // registers. We also need a fast way to compare relative ordering of + // instructions. + // 2. Cache information so this function only has to scan instructions that + // read / def physical instructions. + for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I) { + MachineInstr *MI = I; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isRegister() || MO.getReg() != Reg) + continue; + if (MO.isDef()) + return false; + return true; + } + } + return false; +} + void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { // Does this kill a previous version of this register? if (MachineInstr *LastRef = PhysRegInfo[Reg]) { @@ -338,14 +367,22 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { unsigned SuperReg = *SuperRegs; ++SuperRegs) { if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) { // The larger register is previously defined. Now a smaller part is - // being re-defined. Treat it as read/mod/write. + // being re-defined. Treat it as read/mod/write if there are uses + // below. // EAX = // AX = EAX<imp-use,kill>, EAX<imp-def> - MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/, + // ... + /// = EAX + if (MI && hasRegisterUseBelow(SuperReg, MI, MI->getParent())) { + MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/, true/*IsImp*/,true/*IsKill*/)); - MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/, - true/*IsImp*/)); - PhysRegInfo[SuperReg] = MI; + MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/, + true/*IsImp*/)); + PhysRegInfo[SuperReg] = MI; + } else { + PhysRegInfo[SuperReg]->addRegisterKilled(SuperReg, TRI, true); + PhysRegInfo[SuperReg] = NULL; + } PhysRegUsed[SuperReg] = false; PhysRegPartUse[SuperReg] = NULL; } else { diff --git a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll new file mode 100644 index 0000000000..061c585c74 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger + +define i16 @test(i8* %d1, i16* %d2) { + %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) + ret i16 %tmp237 +} diff --git a/test/CodeGen/X86/x86-64-ret0.ll b/test/CodeGen/X86/x86-64-ret0.ll new file mode 100644 index 0000000000..d4252e7d6e --- /dev/null +++ b/test/CodeGen/X86/x86-64-ret0.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1 + +define i32 @f() nounwind { + tail call void @t( i32 1 ) nounwind + ret i32 0 +} + +declare void @t(i32) |