diff options
| -rw-r--r-- | include/llvm/Target/TargetAsmBackend.h | 10 | ||||
| -rw-r--r-- | lib/MC/MCAssembler.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86AsmBackend.cpp | 13 |
3 files changed, 13 insertions, 12 deletions
diff --git a/include/llvm/Target/TargetAsmBackend.h b/include/llvm/Target/TargetAsmBackend.h index 7a1689d087..979595ad4f 100644 --- a/include/llvm/Target/TargetAsmBackend.h +++ b/include/llvm/Target/TargetAsmBackend.h @@ -16,7 +16,6 @@ namespace llvm { class MCDataFragment; class MCFixup; class MCInst; -class MCInstFragment; class MCObjectWriter; class MCSection; template<typename T> @@ -111,13 +110,16 @@ public: /// MayNeedRelaxation - Check whether the given instruction may need /// relaxation. /// - /// \arg Inst - The instruction to test. + /// \param Inst - The instruction to test. virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0; /// RelaxInstruction - Relax the instruction in the given fragment to the next /// wider instruction. - virtual void RelaxInstruction(const MCInstFragment *IF, - MCInst &Res) const = 0; + /// + /// \param Inst - The instruction to relax, which may be the same as the + /// output. + /// \parm Res [output] - On return, the relaxed instruction. + virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0; /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given /// output. If the target cannot generate such a sequence, it should return an diff --git a/lib/MC/MCAssembler.cpp b/lib/MC/MCAssembler.cpp index 703f727d9d..9c8268df2c 100644 --- a/lib/MC/MCAssembler.cpp +++ b/lib/MC/MCAssembler.cpp @@ -824,7 +824,7 @@ bool MCAssembler::LayoutOnce(MCAsmLayout &Layout) { // Relax the fragment. MCInst Relaxed; - getBackend().RelaxInstruction(IF, Relaxed); + getBackend().RelaxInstruction(IF->getInst(), Relaxed); // Encode the new instruction. // diff --git a/lib/Target/X86/X86AsmBackend.cpp b/lib/Target/X86/X86AsmBackend.cpp index c647713428..151087f58e 100644 --- a/lib/Target/X86/X86AsmBackend.cpp +++ b/lib/Target/X86/X86AsmBackend.cpp @@ -56,7 +56,7 @@ public: bool MayNeedRelaxation(const MCInst &Inst) const; - void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const; + void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; }; @@ -101,20 +101,19 @@ bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const { // FIXME: Can tblgen help at all here to verify there aren't other instructions // we can relax? -void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF, - MCInst &Res) const { +void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. - unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode()); + unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); - if (RelaxedOp == IF->getInst().getOpcode()) { + if (RelaxedOp == Inst.getOpcode()) { SmallString<256> Tmp; raw_svector_ostream OS(Tmp); - IF->getInst().dump_pretty(OS); + Inst.dump_pretty(OS); OS << "\n"; report_fatal_error("unexpected instruction to relax: " + OS.str()); } - Res = IF->getInst(); + Res = Inst; Res.setOpcode(RelaxedOp); } |