diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/X86/zext-shl.ll | 13 |
2 files changed, 11 insertions, 14 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index bec5241ea9..2b52187860 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3291,10 +3291,20 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { if (SCC.getNode()) return SCC; } - // (zext (shl (zext x), y)) -> (shl (zext x), (zext y)) + // (zext (shl (zext x), cst)) -> (shl (zext x), cst) if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && + isa<ConstantSDNode>(N0.getOperand(1)) && N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) { + if (N0.getOpcode() == ISD::SHL) { + // If the original shl may be shifting out bits, do not perform this + // transformation. + unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); + unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - + N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); + if (ShAmt > KnownZeroBits) + return SDValue(); + } DebugLoc dl = N->getDebugLoc(); return DAG.getNode(N0.getOpcode(), dl, VT, DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), diff --git a/test/CodeGen/X86/zext-shl.ll b/test/CodeGen/X86/zext-shl.ll index bc3198a9d1..928848e3f7 100644 --- a/test/CodeGen/X86/zext-shl.ll +++ b/test/CodeGen/X86/zext-shl.ll @@ -23,16 +23,3 @@ entry: %2 = zext i16 %1 to i32 ret i32 %2 } - -define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp { -entry: -; CHECK: t3: -; CHECK: shll -; CHECK-NOT: movzwl -; CHECK: ret - %0 = zext i8 %x to i16 - %1 = zext i8 %y to i16 - %2 = shl i16 %0, %1 - %3 = zext i16 %2 to i32 - ret i32 %3 -} |