diff options
| -rw-r--r-- | docs/ReleaseNotes.html | 5 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 8 |
2 files changed, 4 insertions, 9 deletions
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html index dbeba16455..6159628ecb 100644 --- a/docs/ReleaseNotes.html +++ b/docs/ReleaseNotes.html @@ -337,7 +337,10 @@ Release Notes</a>.</h1> make it run faster:</p> <ul> - <li>....</li> + <li>TableGen can now synthesize register classes that are only needed to + represent combinations of constraints from instructions and sub-registers. + The synthetic register classes inherit most of their properties form their + closest user-defined super-class.</li> </ul> </div> diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 036822d18a..2035b65828 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -326,14 +326,6 @@ def QQPR : RegisterClass<"ARM", [v4i64], 256, (sequence "QQ%u", 0, 7)> { let AltOrderSelect = [{ return 1; }]; } -// Subset of QQPR that have 32-bit SPR subregs. -def QQPR_VFP2 : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 4)> { - let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3), - (DPR_VFP2 dsub_0, dsub_1, dsub_2, dsub_3), - (QPR_VFP2 qsub_0, qsub_1)]; - -} - // Pseudo 512-bit vector register class to model 4 consecutive Q registers // (8 consecutive D registers). def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> { |