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-rw-r--r--lib/Target/ARM/ARM.td3
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp19
-rw-r--r--lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp2
-rw-r--r--test/MC/ARM/arm-thumb-cpus-default.s13
-rw-r--r--test/MC/ARM/arm-thumb-cpus.s20
-rw-r--r--test/MC/ARM/elf-thumbfunc-reloc.s2
-rw-r--r--test/MC/ARM/mapping-within-section.s2
-rw-r--r--test/MC/ARM/multi-section-mapping.s2
8 files changed, 59 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 6e9d62fdea..1bc9d6b410 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -38,7 +38,8 @@ def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
"Enable Thumb2 instructions">;
def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
- "Does not support ARM mode execution">;
+ "Does not support ARM mode execution",
+ [ModeThumb]>;
def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
"Enable half-precision floating point">;
def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ce935b9817..314d37d7d5 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -152,12 +152,19 @@ class ARMAsmParser : public MCTargetAsmParser {
bool isThumbTwo() const {
return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
}
+ bool hasThumb() const {
+ return STI.getFeatureBits() & ARM::HasV4TOps;
+ }
bool hasV6Ops() const {
return STI.getFeatureBits() & ARM::HasV6Ops;
}
bool hasV7Ops() const {
return STI.getFeatureBits() & ARM::HasV7Ops;
}
+ bool hasARM() const {
+ return !(STI.getFeatureBits() & ARM::FeatureNoARM);
+ }
+
void SwitchMode() {
unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
setAvailableFeatures(FB);
@@ -7816,6 +7823,9 @@ bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
return Error(L, "unexpected token in directive");
Parser.Lex();
+ if (!hasThumb())
+ return Error(L, "target does not support Thumb mode");
+
if (!isThumb())
SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
@@ -7829,6 +7839,9 @@ bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
return Error(L, "unexpected token in directive");
Parser.Lex();
+ if (!hasARM())
+ return Error(L, "target does not support ARM mode");
+
if (isThumb())
SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
@@ -7918,10 +7931,16 @@ bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
Parser.Lex();
if (Val == 16) {
+ if (!hasThumb())
+ return Error(L, "target does not support Thumb mode");
+
if (!isThumb())
SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
} else {
+ if (!hasARM())
+ return Error(L, "target does not support ARM mode");
+
if (isThumb())
SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 164f57b2d0..14fd03fad8 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -61,6 +61,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
unsigned SubVer = TT[Idx];
if (SubVer >= '7' && SubVer <= '9') {
if (Len >= Idx+2 && TT[Idx+1] == 'm') {
+ isThumb = true;
if (NoCPU)
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
@@ -99,6 +100,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
ARMArchFeature = "+v6t2";
else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
+ isThumb = true;
if (NoCPU)
// v6m: FeatureNoARM, FeatureMClass
ARMArchFeature = "+v6,+noarm,+mclass";
diff --git a/test/MC/ARM/arm-thumb-cpus-default.s b/test/MC/ARM/arm-thumb-cpus-default.s
new file mode 100644
index 0000000000..636ee3c505
--- /dev/null
+++ b/test/MC/ARM/arm-thumb-cpus-default.s
@@ -0,0 +1,13 @@
+@ RUN: llvm-mc -show-encoding -arch=arm < %s | FileCheck %s --check-prefix=CHECK-ARM-ONLY
+@ RUN: llvm-mc -show-encoding -triple=armv4t < %s | FileCheck %s --check-prefix=CHECK-ARM-THUMB
+@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s| FileCheck %s --check-prefix=CHECK-ARM-THUMB
+@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: llvm-mc -show-encoding -triple=armv7m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: llvm-mc -show-encoding -triple=armv6m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+
+ @ Make sure the architecture chosen by LLVM defaults to a compatible
+ @ ARM/Thumb mode.
+ movs r0, r0
+@ CHECK-ARM-THUMB: movs r0, r0 @ encoding: [0x00,0x00,0xb0,0xe1]
+@ CHECK-ARM-ONLY: movs r0, r0 @ encoding: [0x00,0x00,0xb0,0xe1]
+@ CHECK-THUMB-ONLY: movs r0, r0 @ encoding: [0x00,0x00]
diff --git a/test/MC/ARM/arm-thumb-cpus.s b/test/MC/ARM/arm-thumb-cpus.s
new file mode 100644
index 0000000000..c15e807818
--- /dev/null
+++ b/test/MC/ARM/arm-thumb-cpus.s
@@ -0,0 +1,20 @@
+@ RUN: llvm-mc -show-encoding -arch=arm < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARM-ONLY
+@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB
+@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB
+@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: llvm-mc -show-encoding -triple=armv7m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: llvm-mc -show-encoding -triple=armv6m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+
+ @ Make sure correct diagnostics are given for CPUs without support for
+ @ one or other of the execution states.
+ .thumb
+ .arm
+ .code 16
+ .code 32
+@ CHECK-ARM-THUMB-NOT: target does not support
+
+@ CHECK-ARM-ONLY: target does not support Thumb mode
+@ CHECK-ARM-ONLY: target does not support Thumb mode
+
+@ CHECK-THUMB-ONLY: target does not support ARM mode
+@ CHECK-THUMB-ONLY: target does not support ARM mode
diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s
index de3594e1ce..614702012f 100644
--- a/test/MC/ARM/elf-thumbfunc-reloc.s
+++ b/test/MC/ARM/elf-thumbfunc-reloc.s
@@ -1,5 +1,5 @@
@@ test st_value bit 0 of thumb function
-@ RUN: llvm-mc %s -triple=arm-freebsd-eabi -filetype=obj -o - | \
+@ RUN: llvm-mc %s -triple=armv4t-freebsd-eabi -filetype=obj -o - | \
@ RUN: llvm-readobj -r | FileCheck %s
diff --git a/test/MC/ARM/mapping-within-section.s b/test/MC/ARM/mapping-within-section.s
index 56dd6ef07e..b1379d28a3 100644
--- a/test/MC/ARM/mapping-within-section.s
+++ b/test/MC/ARM/mapping-within-section.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=arm-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
+@ RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
.text
@ $a at 0x0000
diff --git a/test/MC/ARM/multi-section-mapping.s b/test/MC/ARM/multi-section-mapping.s
index f7c4e89a85..2b1b0efab5 100644
--- a/test/MC/ARM/multi-section-mapping.s
+++ b/test/MC/ARM/multi-section-mapping.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=arm-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
+@ RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
.text
add r0, r0, r0
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-08 22:17:49 +0000