diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 5 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 12 | ||||
| -rw-r--r-- | test/CodeGen/ARM/bswap16.ll | 42 |
3 files changed, 59 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 82f203e101..1d2a7e1be4 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4122,6 +4122,11 @@ def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), Requires<[IsARM, HasV6]>, Sched<[WriteALU]>; +def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), + (REV16 (LDRH addrmode3:$addr))>; +def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), + (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; + let AddedComplexity = 5 in def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), IIC_iUNAr, "revsh", "\t$Rd, $Rm", diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 8c58d40e68..170c2ffab5 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -1308,6 +1308,18 @@ def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), (tSUBrr tGPR:$lhs, tGPR:$rhs)>; +// Bswap 16 with load/store +def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rrs2:$addr)), (i32 16)), + (tREV16 (tLDRHr t_addrmode_rrs2:$addr))>; +def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), + (tREV16 (tLDRHi t_addrmode_is2:$addr))>; +def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), + t_addrmode_rrs2:$addr), + (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rrs2:$addr)>; +def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), + t_addrmode_is2:$addr), + (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; + // ConstantPool def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; diff --git a/test/CodeGen/ARM/bswap16.ll b/test/CodeGen/ARM/bswap16.ll new file mode 100644 index 0000000000..29cec4f112 --- /dev/null +++ b/test/CodeGen/ARM/bswap16.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=arm -mattr=v6 < %s | FileCheck %s +; RUN: llc -march=thumb -mattr=v6 < %s | FileCheck %s + + +define void @test1(i16* nocapture %data) { +entry: + %0 = load i16* %data, align 2 + %1 = tail call i16 @llvm.bswap.i16(i16 %0) + store i16 %1, i16* %data, align 2 + ret void + + ; CHECK-LABEL: test1: + ; CHECK: ldrh r[[R1:[0-9]+]], [r0] + ; CHECK: rev16 r[[R1]], r[[R1]] + ; CHECK: strh r[[R1]], [r0] +} + + +define void @test2(i16* nocapture %data, i16 zeroext %in) { +entry: + %0 = tail call i16 @llvm.bswap.i16(i16 %in) + store i16 %0, i16* %data, align 2 + ret void + + ; CHECK-LABEL: test2: + ; CHECK: rev16 r[[R1:[0-9]+]], r1 + ; CHECK: strh r[[R1]], [r0] +} + + +define i16 @test3(i16* nocapture %data) { +entry: + %0 = load i16* %data, align 2 + %1 = tail call i16 @llvm.bswap.i16(i16 %0) + ret i16 %1 + + ; CHECK-LABEL: test3: + ; CHECK: ldrh r[[R0:[0-9]+]], [r0] + ; CHECK: rev16 r[[R0]], r0 +} + +declare i16 @llvm.bswap.i16(i16) |