diff options
| -rw-r--r-- | include/llvm/CodeGen/Passes.h | 3 | ||||
| -rw-r--r-- | lib/CodeGen/MachineLICM.cpp | 9 | ||||
| -rw-r--r-- | lib/CodeGen/Passes.cpp | 2 |
3 files changed, 8 insertions, 6 deletions
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 204898f8d6..bd44bfe0ab 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -93,6 +93,7 @@ public: /// Add the complete, standard set of LLVM CodeGen passes. /// Fully developed targets will not generally override this. virtual void addMachinePasses(); + protected: // Helper to verify the analysis is really immutable. void setOpt(bool &Opt, bool Val); @@ -323,7 +324,7 @@ namespace llvm { /// createMachineLICMPass - This pass performs LICM on machine instructions. /// - FunctionPass *createMachineLICMPass(bool PreRegAlloc = true); + FunctionPass *createMachineLICMPass(); /// createMachineSinkingPass - This pass performs sinking on machine /// instructions. diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 7c07ac4a24..bf6185a7ea 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -60,8 +60,6 @@ STATISTIC(NumPostRAHoisted, namespace { class MachineLICM : public MachineFunctionPass { - bool PreRegAlloc; - const TargetMachine *TM; const TargetInstrInfo *TII; const TargetLowering *TLI; @@ -69,6 +67,7 @@ namespace { const MachineFrameInfo *MFI; MachineRegisterInfo *MRI; const InstrItineraryData *InstrItins; + bool PreRegAlloc; // Various analyses that we use... AliasAnalysis *AA; // Alias analysis info. @@ -298,8 +297,8 @@ INITIALIZE_AG_DEPENDENCY(AliasAnalysis) INITIALIZE_PASS_END(MachineLICM, "machinelicm", "Machine Loop Invariant Code Motion", false, false) -FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) { - return new MachineLICM(PreRegAlloc); +FunctionPass *llvm::createMachineLICMPass() { + return new MachineLICM(); } /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most @@ -332,6 +331,8 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { MRI = &MF.getRegInfo(); InstrItins = TM->getInstrItineraryData(); + PreRegAlloc = MRI->isSSA(); + if (PreRegAlloc) { // Estimate register pressure during pre-regalloc pass. unsigned NumRC = TRI->getNumRegClasses(); diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp index 01662743af..354fedbef9 100644 --- a/lib/CodeGen/Passes.cpp +++ b/lib/CodeGen/Passes.cpp @@ -244,7 +244,7 @@ void TargetPassConfig::addMachinePasses() { // Run post-ra machine LICM to hoist reloads / remats. if (!DisablePostRAMachineLICM) - PM.add(createMachineLICMPass(false)); + PM.add(createMachineLICMPass()); printAndVerify("After StackSlotColoring and postra Machine LICM"); } |