diff options
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.td | 44 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfoV4.td | 36 |
2 files changed, 40 insertions, 40 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index a8824cfe07..8b183b967c 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -98,7 +98,7 @@ let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in multiclass ALU32_Pbase<string mnemonic, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ", @@ -107,7 +107,7 @@ multiclass ALU32_Pbase<string mnemonic, bit isNot, } multiclass ALU32_Pred<string mnemonic, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>; // Predicate new defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>; @@ -144,7 +144,7 @@ defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel; // ALU32/ALU (ADD with register-immediate form) //===----------------------------------------------------------------------===// multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ", @@ -153,7 +153,7 @@ multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> { } multiclass ALU32ri_Pred<string mnemonic, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>; // Predicate new defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>; @@ -222,7 +222,7 @@ def SUB_ri : ALU32_ri<(outs IntRegs:$dst), multiclass TFR_Pred<bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { def _c#NAME : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2", @@ -252,7 +252,7 @@ multiclass TFR_base<string CextOp> { } multiclass TFR64_Pred<bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, DoubleRegs:$src2), !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2", @@ -283,7 +283,7 @@ multiclass TFR64_base<string CextOp> { multiclass TFRI_Pred<bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { def _c#NAME : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Ext:$src2), !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2", @@ -845,16 +845,16 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1, // Load -- MEMri operand multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : LDInst2<(outs RC:$dst), (ins PredRegs:$src1, MEMri:$addr), - #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", ") ")#"$dst = "#mnemonic#"($addr)", []>; } multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>; // Predicate new defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>; @@ -911,17 +911,17 @@ def : Pat < (i64 (load ADDRriS11_3:$addr)), // Load - Base with Immediate offset addressing mode multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : LDInst2<(outs RC:$dst), (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3), - #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", ") ")#"$dst = "#mnemonic#"($src2+#$src3)", []>; } multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>; // Predicate new defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>; @@ -1005,10 +1005,10 @@ def LDd_GP : LDInst2<(outs DoubleRegs:$dst), multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), - #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", ") ")#"$dst = "#mnemonic#"($src2++#$offset)", [], "$src2 = $dst2">; @@ -1016,7 +1016,7 @@ multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp, multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC, Operand ImmOp, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>; // Predicate new let Predicates = [HasV4T], validSubTargets = HasV4SubT in @@ -1440,7 +1440,7 @@ def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst), //===----------------------------------------------------------------------===// multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : STInst2<(outs), (ins PredRegs:$src1, MEMri:$addr, RC: $src2), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", @@ -1449,7 +1449,7 @@ multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot, } multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>; // Predicate new @@ -1467,7 +1467,7 @@ multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC, isPredicable = 1 in def NAME : STInst2<(outs), (ins MEMri:$addr, RC:$src), - #mnemonic#"($addr) = $src", + mnemonic#"($addr) = $src", []>; let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits, @@ -1506,7 +1506,7 @@ def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr), //===----------------------------------------------------------------------===// multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : STInst2<(outs), (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", @@ -1516,7 +1516,7 @@ multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp, multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in { + let PredSense = !if(PredNot, "false", "true"), isPredicated = 1 in { defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>; // Predicate new @@ -1535,7 +1535,7 @@ multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, isPredicable = 1 in def NAME : STInst2<(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - #mnemonic#"($src1+#$src2) = $src3", + mnemonic#"($src1+#$src2) = $src3", []>; let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in { diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index bfe9bb9a76..372de9a8b2 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -418,7 +418,7 @@ def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst), // addressing mode multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : LDInst2<(outs RC:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", @@ -427,7 +427,7 @@ multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot, } multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>; // Predicate new defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>; @@ -1518,7 +1518,7 @@ def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1), // mode multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : STInst2<(outs), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, RC:$src5), @@ -1529,7 +1529,7 @@ multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot, } multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>; // Predicate new defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>; @@ -1542,7 +1542,7 @@ multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> { let isPredicable = 1 in def NAME#_V4 : STInst2<(outs), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4), - #mnemonic#"($src1+$src2<<#$src3) = $src4", + mnemonic#"($src1+$src2<<#$src3) = $src4", []>, Requires<[HasV4T]>; @@ -1557,7 +1557,7 @@ multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> { // addressing mode. multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME#_nv_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, RC:$src5), @@ -1568,7 +1568,7 @@ multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot, } multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>; // Predicate new defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>; @@ -1581,7 +1581,7 @@ multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> { let isPredicable = 1 in def NAME#_nv_V4 : NVInst_V4<(outs), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4), - #mnemonic#"($src1+$src2<<#$src3) = $src4.new", + mnemonic#"($src1+$src2<<#$src3) = $src4.new", []>, Requires<[HasV4T]>; @@ -1682,17 +1682,17 @@ def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst), // addressing mode and immediate stored value. multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME : STInst2<(outs), (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4), - #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", ") ")#mnemonic#"($src2+#$src3) = #$src4", []>, Requires<[HasV4T]>; } multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>; // Predicate new defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>; @@ -1705,7 +1705,7 @@ multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> { let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in def NAME#_V4 : STInst2<(outs), (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3), - #mnemonic#"($src1+#$src2) = #$src3", + mnemonic#"($src1+#$src2) = #$src3", []>, Requires<[HasV4T]>; @@ -2356,7 +2356,7 @@ def : Pat<(store (i32 IntRegs:$src1), // multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC, Operand predImmOp, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME#_nv_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", @@ -2367,7 +2367,7 @@ multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC, multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>; // Predicate new defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>; @@ -2384,7 +2384,7 @@ multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC, isPredicable = 1 in def NAME#_nv_V4 : NVInst_V4<(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - #mnemonic#"($src1+#$src2) = $src3.new", + mnemonic#"($src1+#$src2) = $src3.new", []>, Requires<[HasV4T]>; @@ -2409,7 +2409,7 @@ let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in { // and MEMri operand. multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { - let PNewValue = #!if(isPredNew, "new", "") in + let PNewValue = !if(isPredNew, "new", "") in def NAME#_nv_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, MEMri:$addr, RC: $src2), !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", @@ -2419,7 +2419,7 @@ multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot, } multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> { - let PredSense = #!if(PredNot, "false", "true") in { + let PredSense = !if(PredNot, "false", "true") in { defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>; // Predicate new @@ -2436,7 +2436,7 @@ multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC, isPredicable = 1 in def NAME#_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, RC:$src), - #mnemonic#"($addr) = $src.new", + mnemonic#"($addr) = $src.new", []>, Requires<[HasV4T]>; |