diff options
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 4 | ||||
| -rw-r--r-- | test/MC/AArch64/basic-a64-diagnostics.s | 4 | ||||
| -rw-r--r-- | test/MC/AArch64/basic-a64-instructions.s | 8 |
3 files changed, 12 insertions, 4 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 4091c76fd4..42326fc182 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -1738,6 +1738,10 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> { WZR, GPR32:$src1, GPR32:$src2, 0), 5>; def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs") XZR, GPR64:$src1, GPR64:$src2, 0), 5>; + def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrx") + WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>; + def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrx64") + XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>; // Register/register aliases with no shift when SP is not used. def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"), diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s index 118df368fd..a4a3b1379c 100644 --- a/test/MC/AArch64/basic-a64-diagnostics.s +++ b/test/MC/AArch64/basic-a64-diagnostics.s @@ -395,7 +395,6 @@ cmn w11, w12, lsr #-1 cmn w11, w12, lsr #32 cmn w19, wzr, asr #-1 - cmn wsp, w0 cmn wzr, wzr, asr #32 cmn x9, x10, lsl #-1 cmn x9, x10, lsl #64 @@ -418,9 +417,6 @@ // CHECK-ERROR-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: cmn w19, wzr, asr #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: cmn wsp, w0 -// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] // CHECK-ERROR-NEXT: cmn wzr, wzr, asr #32 // CHECK-ERROR-NEXT: ^ diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s index a12968b04e..8f323982af 100644 --- a/test/MC/AArch64/basic-a64-instructions.s +++ b/test/MC/AArch64/basic-a64-instructions.s @@ -601,9 +601,11 @@ _func: cmn w0, w3 cmn wzr, w4 cmn w5, wzr + cmn wsp, w6 // CHECK: cmn w0, w3 // encoding: [0x1f,0x00,0x03,0x2b] // CHECK: cmn wzr, w4 // encoding: [0xff,0x03,0x04,0x2b] // CHECK: cmn w5, wzr // encoding: [0xbf,0x00,0x1f,0x2b] +// CHECK: cmn wsp, w6 // encoding: [0xff,0x43,0x26,0x2b] cmn w6, w7, lsl #0 cmn w8, w9, lsl #15 @@ -629,9 +631,11 @@ _func: cmn x0, x3 cmn xzr, x4 cmn x5, xzr + cmn sp, x6 // CHECK: cmn x0, x3 // encoding: [0x1f,0x00,0x03,0xab] // CHECK: cmn xzr, x4 // encoding: [0xff,0x03,0x04,0xab] // CHECK: cmn x5, xzr // encoding: [0xbf,0x00,0x1f,0xab] +// CHECK: cmn sp, x6 // encoding: [0xff,0x63,0x26,0xab] cmn x6, x7, lsl #0 cmn x8, x9, lsl #15 @@ -657,9 +661,11 @@ _func: cmp w0, w3 cmp wzr, w4 cmp w5, wzr + cmp wsp, w6 // CHECK: cmp w0, w3 // encoding: [0x1f,0x00,0x03,0x6b] // CHECK: cmp wzr, w4 // encoding: [0xff,0x03,0x04,0x6b] // CHECK: cmp w5, wzr // encoding: [0xbf,0x00,0x1f,0x6b] +// CHECK: cmp wsp, w6 // encoding: [0xff,0x43,0x26,0x6b] cmp w6, w7, lsl #0 cmp w8, w9, lsl #15 @@ -685,9 +691,11 @@ _func: cmp x0, x3 cmp xzr, x4 cmp x5, xzr + cmp sp, x6 // CHECK: cmp x0, x3 // encoding: [0x1f,0x00,0x03,0xeb] // CHECK: cmp xzr, x4 // encoding: [0xff,0x03,0x04,0xeb] // CHECK: cmp x5, xzr // encoding: [0xbf,0x00,0x1f,0xeb] +// CHECK: cmp sp, x6 // encoding: [0xff,0x63,0x26,0xeb] cmp x6, x7, lsl #0 cmp x8, x9, lsl #15 |