summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--include/llvm/CodeGen/ValueTypes.h18
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp27
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp10
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp7
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp3
-rw-r--r--test/CodeGen/X86/2009-02-01-LargeMask.ll32
-rw-r--r--utils/TableGen/CodeGenDAGPatterns.cpp2
7 files changed, 57 insertions, 42 deletions
diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index 2846eb02db..3c6f042536 100644
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -439,24 +439,6 @@ namespace llvm {
else {
return *this;
}
- }
-
- /// getIntegerVTBitMask - Return an integer with 1's every place there are
- /// bits in the specified integer value type. FIXME: Should return an apint.
- uint64_t getIntegerVTBitMask() const {
- assert(isInteger() && "Only applies to integers!");
- MVT EltVT = isVector() ? getVectorElementType() : *this;
- assert(EltVT.getSizeInBits() <= 64 &&
- "getIntegerVTBitMask doesn't use APInt!");
- return ~uint64_t(0UL) >> (64-EltVT.getSizeInBits());
- }
-
- /// getIntegerVTSignBit - Return an integer with a 1 in the position of the
- /// sign bit for the specified integer value type. FIXME: Should return an
- /// apint.
- uint64_t getIntegerVTSignBit() const {
- assert(isInteger() && !isVector() && "Only applies to int scalars!");
- return uint64_t(1UL) << (getSizeInBits()-1);
}
/// getMVTString - This function returns value type as a string,
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index eb433aa880..7d18a864ab 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2498,8 +2498,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(VT.getSizeInBits())))
return DAG.getConstant(0, VT);
- // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
- // iff (trunc c) == c
+ // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND &&
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
@@ -2507,8 +2506,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
MVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
- uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
- N101C->getZExtValue();
+ APInt TruncC = N101C->getAPIntValue();
+ TruncC.trunc(TruncVT.getSizeInBits());
return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
DAG.getNode(ISD::TRUNCATE,
@@ -2632,8 +2631,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
}
}
- // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c))
- // iff (trunc c) == c
+ // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND &&
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
@@ -2641,8 +2639,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
MVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
- uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
- N101C->getZExtValue();
+ APInt TruncC = N101C->getAPIntValue();
+ TruncC.trunc(TruncVT.getSizeInBits());
return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
DAG.getNode(ISD::AND, N->getDebugLoc(),
TruncVT,
@@ -2757,8 +2755,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
}
}
- // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
- // iff (trunc c) == c
+ // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND &&
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
@@ -2766,8 +2763,8 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
MVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
- uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
- N101C->getZExtValue();
+ APInt TruncC = N101C->getAPIntValue();
+ TruncC.trunc(TruncVT.getSizeInBits());
return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
DAG.getNode(ISD::AND, N->getDebugLoc(),
TruncVT,
@@ -4359,8 +4356,8 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
SDValue Int = N0.getOperand(0);
MVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
- Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
- DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
+ Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
+ DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
AddToWorkList(Int.getNode());
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
N->getValueType(0), Int);
@@ -4395,7 +4392,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
MVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
- DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
+ DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
AddToWorkList(Int.getNode());
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
N->getValueType(0), Int);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4dd5dd2542..0b3d979b8e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3110,9 +3110,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
Tmp2, DAG.getIntPtrConstant(i)),
CC);
- Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
- DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
- DAG.getConstant(0, EltVT));
+ Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], DAG.getConstant(
+ APInt::getAllOnesValue(EltVT.getSizeInBits()),
+ EltVT), DAG.getConstant(0, EltVT));
}
Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
break;
@@ -6291,7 +6291,9 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
- SDValue Tmp2 = DAG.getConstant(VT.getIntegerVTBitMask() & mask[i], VT);
+ unsigned EltSize = VT.isVector() ?
+ VT.getVectorElementType().getSizeInBits() : len;
+ SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
DAG.getNode(ISD::AND, VT,
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1b0d61ca0a..d8f895dac2 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -845,12 +845,13 @@ SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
SDValue NegOne;
if (VT.isVector()) {
MVT EltVT = VT.getVectorElementType();
- SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
+ SDValue NegOneElt =
+ getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT);
std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
&NegOnes[0], NegOnes.size());
} else {
- NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
+ NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
}
return getNode(ISD::XOR, DL, VT, Val, NegOne);
@@ -2772,7 +2773,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
return N1;
case ISD::OR:
if (!VT.isVector())
- return getConstant(VT.getIntegerVTBitMask(), VT);
+ return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
// For vectors, we can't easily build an all one vector, just return
// the LHS.
return N1;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 2c79da5bf5..111269f928 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5268,7 +5268,8 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
// bits of the inputs before performing those operations.
if (FlipSigns) {
MVT EltVT = VT.getVectorElementType();
- SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
+ SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
+ EltVT);
std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
SignBits.size());
diff --git a/test/CodeGen/X86/2009-02-01-LargeMask.ll b/test/CodeGen/X86/2009-02-01-LargeMask.ll
new file mode 100644
index 0000000000..f2a964f208
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-01-LargeMask.ll
@@ -0,0 +1,32 @@
+; RUN: llvm-as < %s | llc -march=x86
+; PR3453
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+ %struct.cl_engine = type { i32, i16, i32, i8**, i8**, i8*, i8*, i8*, i8*, i8*, i8*, i8* }
+ %struct.cl_limits = type { i32, i32, i32, i32, i16, i32 }
+ %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
+ %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
+ %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
+ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
+ %struct.cli_ctx = type { i8**, i32*, %struct.cli_matcher*, %struct.cl_engine*, %struct.cl_limits*, i32, i32, i32, i32, %struct.cli_dconf* }
+ %struct.cli_dconf = type { i32, i32, i32, i32, i32, i32, i32 }
+ %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
+
+define fastcc i32 @cli_scanautoit(i32 %desc, %struct.cli_ctx* %ctx, i32 %offset) nounwind {
+entry:
+ br i1 false, label %bb.i49.i72, label %bb14
+
+bb.i49.i72: ; preds = %bb.i49.i72, %entry
+ %UNP.i1482.0 = phi i288 [ %.ins659, %bb.i49.i72 ], [ undef, %entry ] ; <i288> [#uses=1]
+ %0 = load i32* null, align 4 ; <i32> [#uses=1]
+ %1 = xor i32 %0, 17834 ; <i32> [#uses=1]
+ %2 = zext i32 %1 to i288 ; <i288> [#uses=1]
+ %3 = shl i288 %2, 160 ; <i288> [#uses=1]
+ %UNP.i1482.in658.mask = and i288 %UNP.i1482.0, -6277101733925179126504886505003981583386072424808101969921 ; <i288> [#uses=1]
+ %.ins659 = or i288 %3, %UNP.i1482.in658.mask ; <i288> [#uses=1]
+ br label %bb.i49.i72
+
+bb14: ; preds = %entry
+ ret i32 -123
+}
diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp
index e70bdb6f60..f3bdb4fab3 100644
--- a/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -842,7 +842,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// If sign-extended doesn't fit, does it fit as unsigned?
unsigned ValueMask;
unsigned UnsignedVal;
- ValueMask = unsigned(MVT(VT).getIntegerVTBitMask());
+ ValueMask = unsigned(~uint32_t(0UL) >> (32-Size));
UnsignedVal = unsigned(II->getValue());
if ((ValueMask & UnsignedVal) != UnsignedVal) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 03:12:27 +0000