diff options
| -rw-r--r-- | lib/Target/Mips/Mips32r6InstrInfo.td | 24 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips64r6InstrInfo.td | 16 | ||||
| -rw-r--r-- | test/MC/Mips/mips32r6/valid.s | 4 | ||||
| -rw-r--r-- | test/MC/Mips/mips64r6/valid.s | 8 |
4 files changed, 44 insertions, 8 deletions
diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 57bde6fc53..95a22d0052 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -60,6 +60,10 @@ include "Mips32r6InstrFormats.td" // //===----------------------------------------------------------------------===// +class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; +class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; +class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; +class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>; class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; @@ -71,6 +75,18 @@ class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; // //===----------------------------------------------------------------------===// +class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { + dag OutOperandList = (outs GPROpnd:$rd); + dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); + string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); + list<dag> Pattern = []; +} + +class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>; +class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>; +class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>; +class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>; + class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); @@ -125,8 +141,8 @@ def CLASS_D; def CLASS_S; def CMP_CC_D; def CMP_CC_S; -def DIV; // Not to be confused with the old div -def DIVU; // Not to be confused with the old div +def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; +def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; def JIALC; def JIC; // def LSA; // See MSA @@ -140,8 +156,8 @@ def MAX_S; def MINA_D; def MINA_S; def MIN_D; -def MOD; -def MODU; +def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6; +def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6; def MSUBF; def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6; def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index 9607f751aa..e933ecc484 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -25,6 +25,10 @@ // //===----------------------------------------------------------------------===// +class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>; +class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>; +class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>; +class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>; class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>; class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>; class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>; @@ -36,6 +40,10 @@ class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>; // //===----------------------------------------------------------------------===// +class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>; +class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>; +class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>; +class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd>; class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd>; class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd>; class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd>; @@ -52,11 +60,11 @@ def DALIGN; def DATI; def DAUI; def DBITSWAP; -def DDIV; -def DDIVU; +def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; +def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; // def DLSA; // See MSA -def DMOD; -def DMODU; +def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6; +def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6; def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index ad4d322ff3..c822a15466 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -4,6 +4,10 @@ .set noat # FIXME: Add the instructions carried forward from older ISA's + div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] + divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] + modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] # mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 214a8ab53c..fcac87a1fd 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -4,6 +4,14 @@ .set noat # FIXME: Add the instructions carried forward from older ISA's + div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] + divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] + modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] + ddiv $2,$3,$4 # CHECK: ddiv $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9e] + ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f] + dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde] + dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf] # mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] |