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-rw-r--r--include/llvm/CodeGen/MachineInstr.h4
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h7
-rw-r--r--lib/CodeGen/Collector.cpp2
-rw-r--r--lib/CodeGen/MachineInstr.cpp7
-rw-r--r--lib/CodeGen/MachineModuleInfo.cpp2
-rw-r--r--lib/CodeGen/PrologEpilogInserter.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp14
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp16
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp22
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.cpp6
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp8
-rw-r--r--lib/Target/Target.td2
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp8
-rw-r--r--utils/TableGen/DAGISelEmitter.cpp11
15 files changed, 81 insertions, 38 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 5f3838787e..8b0931ac61 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -134,6 +134,10 @@ public:
delete removeFromParent();
}
+ /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
+ ///
+ bool isDebugLabel() const;
+
/// findRegisterUseOperandIdx() - Returns the operand index that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 8d3962e39b..cb4ac72d91 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -496,6 +496,8 @@ namespace ISD {
// returns a chain.
// Operand #0 : input chain.
// Operand #1 : module unique number use to identify the label.
+ // Operand #2 : 0 indicates a debug label (e.g. stoppoint), 1 indicates
+ // a EH label, 2 indicates unknown label type.
LABEL,
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
@@ -593,6 +595,11 @@ namespace ISD {
/// isBuildVectorAllZeros - Return true if the specified node is a
/// BUILD_VECTOR where all of the elements are 0 or undef.
bool isBuildVectorAllZeros(const SDNode *N);
+
+ /// isDebugLabel - Return true if the specified node represents a debug
+ /// label (i.e. ISD::LABEL or TargetInstrInfo::LANEL node and third operand
+ /// is 0).
+ bool isDebugLabel(const SDNode *N);
//===--------------------------------------------------------------------===//
/// MemIndexedMode enum - This enum defines the load / store indexed
diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp
index 1064e59095..fe5119ea2d 100644
--- a/lib/CodeGen/Collector.cpp
+++ b/lib/CodeGen/Collector.cpp
@@ -337,7 +337,7 @@ void MachineCodeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
unsigned Label = MMI->NextLabelID();
- BuildMI(MBB, MI, TII->get(TargetInstrInfo::LABEL)).addImm(Label);
+ BuildMI(MBB, MI, TII->get(TargetInstrInfo::LABEL)).addImm(Label).addImm(2);
return Label;
}
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 8aa854db72..f40ac91e74 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetInstrDesc.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Support/LeakDetector.h"
@@ -512,6 +513,12 @@ unsigned MachineInstr::getNumExplicitOperands() const {
}
+/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
+///
+bool MachineInstr::isDebugLabel() const {
+ return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
+}
+
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.
diff --git a/lib/CodeGen/MachineModuleInfo.cpp b/lib/CodeGen/MachineModuleInfo.cpp
index 80bedd0ad7..12680a0e9c 100644
--- a/lib/CodeGen/MachineModuleInfo.cpp
+++ b/lib/CodeGen/MachineModuleInfo.cpp
@@ -1914,7 +1914,7 @@ bool DebugLabelFolder::runOnMachineFunction(MachineFunction &MF) {
// Iterate through instructions.
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
// Is it a label.
- if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
+ if (I->isDebugLabel()) {
// The label ID # is always operand #0, an immediate.
unsigned NextLabel = I->getOperand(0).getImm();
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index c990ba4776..34cbb2b077 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -253,7 +253,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
// entry block.
MachineModuleInfo *MMI = FFI->getMachineModuleInfo();
if (MMI && MMI->hasDebugInfo())
- while (I != MBB->end() && I->getOpcode() == TargetInstrInfo::LABEL)
+ while (I != MBB->end() && I->isDebugLabel())
++I;
if (!TII.spillCalleeSavedRegisters(*MBB, I, CSI)) {
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 1dbcf8529d..9a4bec2acc 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1060,7 +1060,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
+ Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
+ Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
}
} else {
Result = Tmp1; // chain
@@ -1103,13 +1104,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break;
case ISD::LABEL:
- assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
+ assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+ Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
break;
case TargetLowering::Expand:
Result = LegalizeOp(Node->getOperand(0));
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index c9fc812259..ac35b40d92 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -733,18 +733,16 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
}
// Now that we have emitted all operands, emit this instruction itself.
- if (Opc == TargetInstrInfo::LABEL &&
+ if (ISD::isDebugLabel(Node) &&
!BB->empty() && &MF->front() == BB) {
- // If we are inserting a LABEL and this happens to be the first label in
- // the entry block, it is the "function start" label. Make sure there are
- // no other instructions before it.
+ // If we are inserting a debug label and this happens to be the first
+ // debug label in the entry block, it is the "function start" label.
+ // Make sure there are no other instructions before it.
unsigned NumLabels = 0;
MachineBasicBlock::iterator MBBI = BB->begin();
while (MBBI != BB->end()) {
- if (MBBI->getOpcode() == TargetInstrInfo::LABEL) {
- if (++NumLabels > 1)
- break;
- }
+ if (!MBBI->isDebugLabel() || ++NumLabels > 1)
+ break;
++MBBI;
}
if (NumLabels <= 1)
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 118f980c10..28d7006ac9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -173,6 +173,22 @@ bool ISD::isBuildVectorAllZeros(const SDNode *N) {
return true;
}
+/// isDebugLabel - Return true if the specified node represents a debug
+/// label (i.e. ISD::LABEL or TargetInstrInfo::LANEL node and third operand
+/// is 0).
+bool ISD::isDebugLabel(const SDNode *N) {
+ SDOperand Zero;
+ if (N->getOpcode() == ISD::LABEL)
+ Zero = N->getOperand(2);
+ else if (N->isTargetOpcode() &&
+ N->getTargetOpcode() == TargetInstrInfo::LABEL)
+ // Chain moved to last operand.
+ Zero = N->getOperand(1);
+ else
+ return false;
+ return isa<ConstantSDNode>(Zero) && cast<ConstantSDNode>(Zero)->isNullValue();
+}
+
/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
/// when given the operation for (X op Y).
ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 04c4e0153e..4d1e7ebefb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2621,7 +2621,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(LabelID, MVT::i32)));
+ DAG.getConstant(LabelID, MVT::i32),
+ DAG.getConstant(0, MVT::i32)));
}
return 0;
@@ -2631,8 +2632,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
- getRoot(), DAG.getConstant(LabelID, MVT::i32)));
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+ DAG.getConstant(LabelID, MVT::i32),
+ DAG.getConstant(0, MVT::i32)));
}
return 0;
@@ -2643,8 +2645,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
if (MMI && FSI.getSubprogram() &&
MMI->Verify(FSI.getSubprogram())) {
unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
- getRoot(), DAG.getConstant(LabelID, MVT::i32)));
+ DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
+ DAG.getConstant(LabelID, MVT::i32),
+ DAG.getConstant(0, MVT::i32)));
}
return 0;
@@ -2972,7 +2975,8 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
// used to detect deletion of the invoke via the MachineModuleInfo.
BeginLabel = MMI->NextLabelID();
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(BeginLabel, MVT::i32)));
+ DAG.getConstant(BeginLabel, MVT::i32),
+ DAG.getConstant(1, MVT::i32)));
}
std::pair<SDOperand,SDOperand> Result =
@@ -2989,7 +2993,8 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
// can be used to detect deletion of the invoke via the MachineModuleInfo.
EndLabel = MMI->NextLabelID();
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(EndLabel, MVT::i32)));
+ DAG.getConstant(EndLabel, MVT::i32),
+ DAG.getConstant(1, MVT::i32)));
// Inform MachineModuleInfo of range.
MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
@@ -4573,7 +4578,8 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
// landing pad can thus be detected via the MachineModuleInfo.
unsigned LabelID = MMI->addLandingPad(BB);
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
- DAG.getConstant(LabelID, MVT::i32)));
+ DAG.getConstant(LabelID, MVT::i32),
+ DAG.getConstant(1, MVT::i32)));
// Mark exception register as live in.
unsigned Reg = TLI.getExceptionAddressRegister();
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 3c89c7f306..39edccb606 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -454,7 +454,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0);
}
// Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
@@ -514,7 +514,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0);
MachineLocation FPDst(SPU::R1);
MachineLocation FPSrc(MachineLocation::VirtualFP);
@@ -528,7 +528,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
MachineBasicBlock::iterator MBBI = prior(MBB.end());
// Insert terminator label
unsigned BranchLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId);
+ BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
}
}
}
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index ff8b359470..fa218263bc 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -712,11 +712,11 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Prepare for frame info.
unsigned FrameLabelId = 0;
- // Skip over the labels which mark the beginning of the function.
+ // Skip over the debug labels which mark the beginning of the function.
if (MMI && MMI->needsFrameInfo()) {
unsigned NumLabels = 0;
while (NumLabels <= 1 &&
- MBBI != MBB.end() && MBBI->getOpcode() == PPC::LABEL) {
+ MBBI != MBB.end() && MBBI->isDebugLabel()) {
++NumLabels;
++MBBI;
}
@@ -786,7 +786,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (MMI && MMI->needsFrameInfo()) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
}
// Adjust stack pointer: r1 += NegFrameSize.
@@ -870,7 +870,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index d155e713c0..4b1ab2850c 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -334,7 +334,7 @@ def INLINEASM : Instruction {
}
def LABEL : Instruction {
let OutOperandList = (ops);
- let InOperandList = (ops i32imm:$id);
+ let InOperandList = (ops i32imm:$id, i32imm:$flavor);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 53efdc8d55..5f9f290ae7 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -525,11 +525,11 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
- // Skip over the labels which mark the beginning of the function.
+ // Skip over the debug labels which mark the beginning of the function.
if (MMI && MMI->needsFrameInfo()) {
unsigned NumLabels = 0;
while (NumLabels <= 1 &&
- MBBI != MBB.end() && MBBI->getOpcode() == X86::LABEL) {
+ MBBI != MBB.end() && MBBI->isDebugLabel()) {
++NumLabels;
++MBBI;
}
@@ -557,7 +557,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
if (MMI && MMI->needsFrameInfo()) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
}
// Update EBP with the new base value...
@@ -569,7 +569,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
if (MMI && MMI->needsFrameInfo()) {
// Mark effective beginning of when frame pointer is ready.
ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
}
// Skip the callee-saved push instructions.
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index 1f568ad5ee..05c27c47d9 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -1795,12 +1795,15 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
OS << "SDNode *Select_LABEL(const SDOperand &N) {\n"
<< " SDOperand Chain = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
- << " unsigned C = cast<ConstantSDNode>(N1)->getValue();\n"
- << " SDOperand Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
+ << " SDOperand N2 = N.getOperand(2);\n"
+ << " unsigned C1 = cast<ConstantSDNode>(N1)->getValue();\n"
+ << " unsigned C2 = cast<ConstantSDNode>(N2)->getValue();\n"
+ << " SDOperand Tmp1 = CurDAG->getTargetConstant(C1, MVT::i32);\n"
+ << " SDOperand Tmp2 = CurDAG->getTargetConstant(C2, MVT::i32);\n"
<< " AddToISelQueue(Chain);\n"
- << " SDOperand Ops[] = { Tmp, Chain };\n"
+ << " SDOperand Ops[] = { Tmp1, Tmp2, Chain };\n"
<< " return CurDAG->getTargetNode(TargetInstrInfo::LABEL,\n"
- << " MVT::Other, Ops, 2);\n"
+ << " MVT::Other, Ops, 3);\n"
<< "}\n\n";
OS << "SDNode *Select_EXTRACT_SUBREG(const SDOperand &N) {\n"
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 00:26:55 +0000