diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 42 |
1 files changed, 17 insertions, 25 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 22716e3477..886ff05491 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -799,21 +799,16 @@ class VLD1DUP<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "", [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6:$Rn)))))]> { let Rm = 0b1111; + let Inst{4} = Rn{4}; } class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> { let Pattern = [(set QPR:$dst, (Ty (NEONvdup (i32 (LoadOp addrmode6:$addr)))))]; } -def VLD1DUPd8 : VLD1DUP<0b1100, {0,0,0,?}, "8", v8i8, extloadi8> { - let Inst{4} = Rn{4}; -} -def VLD1DUPd16 : VLD1DUP<0b1100, {0,1,0,?}, "16", v4i16, extloadi16> { - let Inst{4} = Rn{4}; -} -def VLD1DUPd32 : VLD1DUP<0b1100, {1,0,0,?}, "32", v2i32, load> { - let Inst{4} = Rn{4}; -} +def VLD1DUPd8 : VLD1DUP<0b1100, {0,0,0,?}, "8", v8i8, extloadi8>; +def VLD1DUPd16 : VLD1DUP<0b1100, {0,1,0,?}, "16", v4i16, extloadi16>; +def VLD1DUPd32 : VLD1DUP<0b1100, {1,0,0,?}, "32", v2i32, load>; def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>; def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>; @@ -827,37 +822,34 @@ class VLD1QDUP<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, (ins addrmode6:$Rn), IIC_VLD1dup, "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> { let Rm = 0b1111; + let Inst{4} = Rn{4}; } def VLD1DUPq8 : VLD1QDUP<0b1100, {0,0,1,0}, "8", v16i8, extloadi8>; -def VLD1DUPq16 : VLD1QDUP<0b1100, {0,1,1,?}, "16", v8i16, extloadi16> { - let Inst{4} = Rn{4}; -} -def VLD1DUPq32 : VLD1QDUP<0b1100, {1,0,1,?}, "32", v4i32, load> { - let Inst{4} = Rn{4}; -} +def VLD1DUPq16 : VLD1QDUP<0b1100, {0,1,1,?}, "16", v8i16, extloadi16>; +def VLD1DUPq32 : VLD1QDUP<0b1100, {1,0,1,?}, "32", v4i32, load>; // ...with address register writeback: class VLD1DUPWB<bits<4> op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu, - "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []>; + "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} class VLD1QDUPWB<bits<4> op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu, - "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []>; + "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { + let Inst{4} = Rn{4}; +} def VLD1DUPd8_UPD : VLD1DUPWB<0b1100, {0,0,0,0}, "8">; -def VLD1DUPd16_UPD : VLD1DUPWB<0b1100, {0,1,0,?}, "16"> { let Inst{4} = Rn{4}; } -def VLD1DUPd32_UPD : VLD1DUPWB<0b1100, {1,0,0,?}, "32"> { let Inst{4} = Rn{4}; } +def VLD1DUPd16_UPD : VLD1DUPWB<0b1100, {0,1,0,?}, "16">; +def VLD1DUPd32_UPD : VLD1DUPWB<0b1100, {1,0,0,?}, "32">; def VLD1DUPq8_UPD : VLD1QDUPWB<0b1100, {0,0,1,0}, "8">; -def VLD1DUPq16_UPD : VLD1QDUPWB<0b1100, {0,1,1,?}, "16"> { - let Inst{4} = Rn{4}; -} -def VLD1DUPq32_UPD : VLD1QDUPWB<0b1100, {1,0,1,?}, "32"> { - let Inst{4} = Rn{4}; -} +def VLD1DUPq16_UPD : VLD1QDUPWB<0b1100, {0,1,1,?}, "16">; +def VLD1DUPq32_UPD : VLD1QDUPWB<0b1100, {1,0,1,?}, "32">; def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>; def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>; |