diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/Thumb/2011-06-16-NoGPRs.ll | 24 |
2 files changed, 31 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index e439347228..2a65d65f4f 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -76,6 +76,12 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, // the CopyToReg'd destination register instead of creating a new vreg. bool MatchReg = true; const TargetRegisterClass *UseRC = NULL; + EVT VT = Node->getValueType(ResNo); + + // Stick to the preferred register classes for legal types. + if (TLI->isTypeLegal(VT)) + UseRC = TLI->getRegClassFor(VT); + if (!IsClone && !IsCloned) for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); UI != E; ++UI) { @@ -121,10 +127,9 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, break; } - EVT VT = Node->getValueType(ResNo); const TargetRegisterClass *SrcRC = 0, *DstRC = 0; SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); - + // Figure out the register class to create for the destreg. if (VRBase) { DstRC = MRI->getRegClass(VRBase); diff --git a/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll b/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll new file mode 100644 index 0000000000..d39a76085a --- /dev/null +++ b/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s +; +; This test would crash because isel creates a GPR register for the return +; value from f1. The register is only used by tBLXr_r9 which accepts a full GPR +; register, but we cannot have live GPRs in thumb mode because we don't know how +; to spill them. +; +; <rdar://problem/9624323> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv6-apple-darwin10" + +%0 = type opaque + +declare i8* (i8*, i8*, ...)* @f1(i8*, i8*) optsize +declare i8* @f2(i8*, i8*, ...) + +define internal void @f(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize ssp { +entry: + %call14 = tail call i8* (i8*, i8*, ...)* (i8*, i8*)* @f1(i8* undef, i8* %_cmd) optsize + %0 = bitcast i8* (i8*, i8*, ...)* %call14 to void (i8*, i8*, %0*, %0*)* + tail call void %0(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize + tail call void bitcast (i8* (i8*, i8*, ...)* @f2 to void (i8*, i8*, i32, %0*, %0*)*)(i8* %self, i8* undef, i32 2, %0* %inIndexes, %0* undef) optsize + ret void +} |