diff options
| -rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 12 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonTargetMachine.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/R600/AMDGPUTargetMachine.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86TargetMachine.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreTargetMachine.cpp | 2 |
5 files changed, 16 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 0bc0fa2a54..0c9e0a4720 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -71,6 +71,11 @@ static std::string computeDataLayout(ARMSubtarget &ST) { // Little endian. Pointers are 32 bits and aligned to 32 bits. std::string Ret = "e-p:32:32"; + // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to + // align to 32. + if (ST.isThumb()) + Ret += "-i1:8:32-i8:8:32-i16:16:32"; + // We have 64 bits floats and integers. The APCS ABI requires them to be // aligned s them to 32 bits, others to 64 bits. We always try to align to // 64 bits. @@ -79,15 +84,10 @@ static std::string computeDataLayout(ARMSubtarget &ST) { else Ret += "-i64:64"; - // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to - // align to 32. - if (ST.isThumb()) - Ret += "-i16:16:32-i8:8:32-i1:8:32"; - // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others // to 64. We always ty to give them natural alignment. if (ST.isAPCS_ABI()) - Ret += "-v128:32:128-v64:32:64"; + Ret += "-v64:32:64-v128:32:128"; else Ret += "-v128:64:128"; diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 2be0a7ab65..1261594e51 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -71,7 +71,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - DL("e-p:32:32-i64:64-i1:32-a:0-n32") , + DL("e-p:32:32-i1:32-i64:64-a:0-n32") , Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget), diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 521422e7b4..89c27839ab 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -50,8 +50,7 @@ SchedCustomRegistry("r600", "Run R600's custom scheduler", createR600MachineScheduler); static std::string computeDataLayout(const AMDGPUSubtarget &ST) { - std::string Ret = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256" - "-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; + std::string Ret = "e"; if (!ST.is64bit()) Ret += "-p:32:32"; @@ -59,6 +58,9 @@ static std::string computeDataLayout(const AMDGPUSubtarget &ST) { if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) Ret += "-p3:32:32"; + Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256" + "-v512:512-v1024:1024-v2048:2048-n32:64"; + return Ret; } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 2165aefab5..64816e413c 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -38,11 +38,6 @@ static std::string computeDataLayout(const X86Subtarget &ST) { if (ST.isTarget64BitILP32() || !ST.is64Bit()) Ret += "-p:32:32"; - // Objects on the stack ore aligned to 64 bits. - // FIXME: of any size? - if (ST.is64Bit()) - Ret += "-s:64"; - // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32. if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows()) Ret += "-i64:64"; @@ -55,6 +50,10 @@ static std::string computeDataLayout(const X86Subtarget &ST) { else Ret += "-f80:32"; + // Objects on the stack ore aligned to 64 bits. + if (ST.is64Bit()) + Ret += "-s:64"; + // The registers can hold 8, 16, 32 or, in x86-64, 64 bits. if (ST.is64Bit()) Ret += "-n8:16:32:64"; diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index c01d5e9b5c..4d24736cc0 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -27,7 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), Subtarget(TT, CPU, FS), - DL("e-p:32:32-a:0:32-f64:32-i1:8:32-i8:8:32-i16:16:32-i64:32-n32"), + DL("e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32"), InstrInfo(), FrameLowering(Subtarget), TLInfo(*this), |