diff options
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-VCVT-arm.txt | 8 |
2 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 824ffbf338..0b93f91054 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4441,7 +4441,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); } - if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); + if (!(imm & 0x20)) return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; @@ -4469,7 +4469,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); } - if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); + if (!(imm & 0x20)) return MCDisassembler::Fail; if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler::Fail; diff --git a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt b/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt new file mode 100644 index 0000000000..113507c4ec --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt @@ -0,0 +1,8 @@ +# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD) +# imm6=0b0xxxxx -> UNDEFINED + +# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s + +# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding |