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-rw-r--r--lib/Target/SystemZ/SystemZInstrInfo.td14
-rw-r--r--test/CodeGen/SystemZ/int-add-08.ll3
-rw-r--r--test/CodeGen/SystemZ/int-add-09.ll2
-rw-r--r--test/CodeGen/SystemZ/int-add-16.ll22
-rw-r--r--test/CodeGen/SystemZ/int-sub-05.ll5
-rw-r--r--test/CodeGen/SystemZ/int-sub-09.ll22
-rw-r--r--test/MC/Disassembler/SystemZ/insns.txt24
-rw-r--r--test/MC/SystemZ/insn-bad.s20
-rw-r--r--test/MC/SystemZ/insn-good-z196.s48
9 files changed, 152 insertions, 8 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 5ffb86b32e..56b7a1f63b 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -564,11 +564,17 @@ defm : SXB<add, GR64, AGFR>;
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
- def ALR : BinaryRR <"al", 0x1E, addc, GR32, GR32>;
- def ALGR : BinaryRRE<"alg", 0xB90A, addc, GR64, GR64>;
+ defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
+ defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
}
def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
+ // Addition of signed 16-bit immediates.
+ def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
+ Requires<[FeatureDistinctOps]>;
+ def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
+ Requires<[FeatureDistinctOps]>;
+
// Addition of unsigned 32-bit immediates.
def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
@@ -614,9 +620,9 @@ defm : SXB<sub, GR64, SGFR>;
// Subtraction producing a carry.
let Defs = [CC] in {
// Subtraction of a register.
- def SLR : BinaryRR <"sl", 0x1F, subc, GR32, GR32>;
+ defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
- def SLGR : BinaryRRE<"slg", 0xB90B, subc, GR64, GR64>;
+ defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
// Subtraction of unsigned 32-bit immediates. These don't match
// subc because we prefer addc for constants.
diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll
index d645137e5f..bcef914ed8 100644
--- a/test/CodeGen/SystemZ/int-add-08.ll
+++ b/test/CodeGen/SystemZ/int-add-08.ll
@@ -1,6 +1,7 @@
; Test 128-bit addition in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i128 *@foo()
diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll
index 43136bde33..717fed00e2 100644
--- a/test/CodeGen/SystemZ/int-add-09.ll
+++ b/test/CodeGen/SystemZ/int-add-09.ll
@@ -1,6 +1,6 @@
; Test 128-bit addition in which the second operand is constant.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check additions of 1. The XOR ensures that we don't instead load the
; constant into a register and use memory addition.
diff --git a/test/CodeGen/SystemZ/int-add-16.ll b/test/CodeGen/SystemZ/int-add-16.ll
new file mode 100644
index 0000000000..409729f089
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-add-16.ll
@@ -0,0 +1,22 @@
+; Test 128-bit addition when the distinct-operands facility is available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test the case where both operands are in registers.
+define i64 @f1(i64 %a, i64 %b, i64 %c, i64 %d, i64 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: algrk %r2, %r4, %r5
+; CHECK: alcgr
+; CHECK: br %r14
+ %x1 = insertelement <2 x i64> undef, i64 %b, i32 0
+ %x2 = insertelement <2 x i64> %x1, i64 %c, i32 1
+ %x = bitcast <2 x i64> %x2 to i128
+ %y2 = insertelement <2 x i64> %x1, i64 %d, i32 1
+ %y = bitcast <2 x i64> %y2 to i128
+ %add = add i128 %x, %y
+ %addv = bitcast i128 %add to <2 x i64>
+ %high = extractelement <2 x i64> %addv, i32 0
+ store i64 %high, i64 *%ptr
+ %low = extractelement <2 x i64> %addv, i32 1
+ ret i64 %low
+}
diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll
index 9ec66d090f..85ea14cd15 100644
--- a/test/CodeGen/SystemZ/int-sub-05.ll
+++ b/test/CodeGen/SystemZ/int-sub-05.ll
@@ -1,6 +1,7 @@
-; Test 128-bit addition in which the second operand is variable.
+; Test 128-bit subtraction in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i128 *@foo()
diff --git a/test/CodeGen/SystemZ/int-sub-09.ll b/test/CodeGen/SystemZ/int-sub-09.ll
new file mode 100644
index 0000000000..00a60d3819
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-sub-09.ll
@@ -0,0 +1,22 @@
+; Test 128-bit subtraction when the distinct-operands facility is available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test the case where both operands are in registers.
+define i64 @f1(i64 %a, i64 %b, i64 %c, i64 %d, i64 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: slgrk %r2, %r4, %r5
+; CHECK: slbgr
+; CHECK: br %r14
+ %x1 = insertelement <2 x i64> undef, i64 %b, i32 0
+ %x2 = insertelement <2 x i64> %x1, i64 %c, i32 1
+ %x = bitcast <2 x i64> %x2 to i128
+ %y2 = insertelement <2 x i64> %x1, i64 %d, i32 1
+ %y = bitcast <2 x i64> %y2 to i128
+ %sub = sub i128 %x, %y
+ %subv = bitcast i128 %sub to <2 x i64>
+ %high = extractelement <2 x i64> %subv, i32 0
+ store i64 %high, i64 *%ptr
+ %low = extractelement <2 x i64> %subv, i32 1
+ ret i64 %low
+}
diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt
index e91be56b5c..6e0c2559b2 100644
--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
@@ -505,6 +505,12 @@
# CHECK: algr %r7, %r8
0xb9 0x0a 0x00 0x78
+# CHECK: algrk %r0, %r0, %r0
+0xb9 0xea 0x00 0x00
+
+# CHECK: algrk %r2, %r3, %r4
+0xb9 0xea 0x40 0x23
+
# CHECK: alg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x0a
@@ -547,6 +553,12 @@
# CHECK: alr %r7, %r8
0x1e 0x78
+# CHECK: alrk %r0, %r0, %r0
+0xb9 0xfa 0x00 0x00
+
+# CHECK: alrk %r2, %r3, %r4
+0xb9 0xfa 0x40 0x23
+
# CHECK: al %r0, 0
0x5e 0x00 0x00 0x00
@@ -5221,6 +5233,12 @@
# CHECK: slgr %r7, %r8
0xb9 0x0b 0x00 0x78
+# CHECK: slgrk %r0, %r0, %r0
+0xb9 0xeb 0x00 0x00
+
+# CHECK: slgrk %r2, %r3, %r4
+0xb9 0xeb 0x40 0x23
+
# CHECK: slg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x0b
@@ -5359,6 +5377,12 @@
# CHECK: slr %r7, %r8
0x1f 0x78
+# CHECK: slrk %r0, %r0, %r0
+0xb9 0xfb 0x00 0x00
+
+# CHECK: slrk %r2, %r3, %r4
+0xb9 0xfb 0x40 0x23
+
# CHECK: sl %r0, 0
0x5f 0x00 0x00 0x00
diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s
index f0a8e414b1..4caa5dc74a 100644
--- a/test/MC/SystemZ/insn-bad.s
+++ b/test/MC/SystemZ/insn-bad.s
@@ -184,6 +184,16 @@
algfi %r0, -1
algfi %r0, (1 << 32)
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: algrk %r2,%r3,%r4
+
+ algrk %r2,%r3,%r4
+
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: alrk %r2,%r3,%r4
+
+ alrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: aly %r0, -524289
#CHECK: error: invalid operand
@@ -2361,6 +2371,11 @@
slgfi %r0, -1
slgfi %r0, (1 << 32)
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: slgrk %r2,%r3,%r4
+
+ slgrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: sll %r0,-1
#CHECK: error: invalid operand
@@ -2394,6 +2409,11 @@
sllk %r2,%r3,4(%r5)
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: slrk %r2,%r3,%r4
+
+ slrk %r2,%r3,%r4
+
#CHECK: error: invalid operand
#CHECK: sly %r0, -524289
#CHECK: error: invalid operand
diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s
index 6bfb7e862b..7a686a3f25 100644
--- a/test/MC/SystemZ/insn-good-z196.s
+++ b/test/MC/SystemZ/insn-good-z196.s
@@ -49,6 +49,30 @@
ahik %r15, %r0, 0
ahik %r7, %r8, -16
+#CHECK: algrk %r0, %r0, %r0 # encoding: [0xb9,0xea,0x00,0x00]
+#CHECK: algrk %r0, %r0, %r15 # encoding: [0xb9,0xea,0xf0,0x00]
+#CHECK: algrk %r0, %r15, %r0 # encoding: [0xb9,0xea,0x00,0x0f]
+#CHECK: algrk %r15, %r0, %r0 # encoding: [0xb9,0xea,0x00,0xf0]
+#CHECK: algrk %r7, %r8, %r9 # encoding: [0xb9,0xea,0x90,0x78]
+
+ algrk %r0,%r0,%r0
+ algrk %r0,%r0,%r15
+ algrk %r0,%r15,%r0
+ algrk %r15,%r0,%r0
+ algrk %r7,%r8,%r9
+
+#CHECK: alrk %r0, %r0, %r0 # encoding: [0xb9,0xfa,0x00,0x00]
+#CHECK: alrk %r0, %r0, %r15 # encoding: [0xb9,0xfa,0xf0,0x00]
+#CHECK: alrk %r0, %r15, %r0 # encoding: [0xb9,0xfa,0x00,0x0f]
+#CHECK: alrk %r15, %r0, %r0 # encoding: [0xb9,0xfa,0x00,0xf0]
+#CHECK: alrk %r7, %r8, %r9 # encoding: [0xb9,0xfa,0x90,0x78]
+
+ alrk %r0,%r0,%r0
+ alrk %r0,%r0,%r15
+ alrk %r0,%r15,%r0
+ alrk %r15,%r0,%r0
+ alrk %r7,%r8,%r9
+
#CHECK: ark %r0, %r0, %r0 # encoding: [0xb9,0xf8,0x00,0x00]
#CHECK: ark %r0, %r0, %r15 # encoding: [0xb9,0xf8,0xf0,0x00]
#CHECK: ark %r0, %r15, %r0 # encoding: [0xb9,0xf8,0x00,0x0f]
@@ -121,6 +145,30 @@
sgrk %r15,%r0,%r0
sgrk %r7,%r8,%r9
+#CHECK: slgrk %r0, %r0, %r0 # encoding: [0xb9,0xeb,0x00,0x00]
+#CHECK: slgrk %r0, %r0, %r15 # encoding: [0xb9,0xeb,0xf0,0x00]
+#CHECK: slgrk %r0, %r15, %r0 # encoding: [0xb9,0xeb,0x00,0x0f]
+#CHECK: slgrk %r15, %r0, %r0 # encoding: [0xb9,0xeb,0x00,0xf0]
+#CHECK: slgrk %r7, %r8, %r9 # encoding: [0xb9,0xeb,0x90,0x78]
+
+ slgrk %r0,%r0,%r0
+ slgrk %r0,%r0,%r15
+ slgrk %r0,%r15,%r0
+ slgrk %r15,%r0,%r0
+ slgrk %r7,%r8,%r9
+
+#CHECK: slrk %r0, %r0, %r0 # encoding: [0xb9,0xfb,0x00,0x00]
+#CHECK: slrk %r0, %r0, %r15 # encoding: [0xb9,0xfb,0xf0,0x00]
+#CHECK: slrk %r0, %r15, %r0 # encoding: [0xb9,0xfb,0x00,0x0f]
+#CHECK: slrk %r15, %r0, %r0 # encoding: [0xb9,0xfb,0x00,0xf0]
+#CHECK: slrk %r7, %r8, %r9 # encoding: [0xb9,0xfb,0x90,0x78]
+
+ slrk %r0,%r0,%r0
+ slrk %r0,%r0,%r15
+ slrk %r0,%r15,%r0
+ slrk %r15,%r0,%r0
+ slrk %r7,%r8,%r9
+
#CHECK: sllk %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdf]
#CHECK: sllk %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdf]
#CHECK: sllk %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdf]
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 19:53:24 +0000