diff options
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/msa/arithmetic_float.ll | 44 |
3 files changed, 51 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 4a95bc5704..f1d19a9481 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1797,10 +1797,8 @@ class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; -class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", int_mips_fmadd_w, - MSA128WOpnd>; -class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", int_mips_fmadd_d, - MSA128DOpnd>; +class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; +class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index a08d157fed..96c0843811 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -223,6 +223,7 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::FADD, Ty, Legal); setOperationAction(ISD::FDIV, Ty, Legal); setOperationAction(ISD::FLOG2, Ty, Legal); + setOperationAction(ISD::FMA, Ty, Legal); setOperationAction(ISD::FMUL, Ty, Legal); setOperationAction(ISD::FRINT, Ty, Legal); setOperationAction(ISD::FSQRT, Ty, Legal); @@ -1332,6 +1333,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_flog2_w: case Intrinsic::mips_flog2_d: return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fmadd_w: + case Intrinsic::mips_fmadd_d: + return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), + Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); case Intrinsic::mips_fmul_w: case Intrinsic::mips_fmul_d: return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index 82e05ad8f9..70167effff 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -96,6 +96,46 @@ define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nou ; CHECK: .size mul_v2f64 } +define void @fma_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, + <4 x float>* %c) nounwind { + ; CHECK: fma_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x float>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = load <4 x float>* %c + ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) + %4 = tail call <4 x float> @llvm.fma.v4f32 (<4 x float> %1, <4 x float> %2, + <4 x float> %3) + ; CHECK-DAG: fmadd.w [[R1]], [[R2]], [[R3]] + store <4 x float> %4, <4 x float>* %d + ; CHECK-DAG: st.w [[R1]], 0($4) + + ret void + ; CHECK: .size fma_v4f32 +} + +define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, + <2 x double>* %c) nounwind { + ; CHECK: fma_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x double>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = load <2 x double>* %c + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) + %4 = tail call <2 x double> @llvm.fma.v2f64 (<2 x double> %1, <2 x double> %2, + <2 x double> %3) + ; CHECK-DAG: fmadd.d [[R1]], [[R2]], [[R3]] + store <2 x double> %4, <2 x double>* %d + ; CHECK-DAG: st.d [[R1]], 0($4) + + ret void + ; CHECK: .size fma_v2f64 +} + define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { ; CHECK: fdiv_v4f32: @@ -298,5 +338,9 @@ define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind { declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val) declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val) +declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, + <4 x float> %c) +declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b, + <2 x double> %c) declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val) declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val) |