diff options
| -rw-r--r-- | lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcInstrAliases.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/2011-01-11-FrameAddr.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/2011-01-19-DelaySlot.ll | 6 | ||||
| -rw-r--r-- | test/MC/Disassembler/Sparc/sparc.txt | 3 | ||||
| -rw-r--r-- | test/MC/Sparc/sparc-alu-instructions.s | 3 |
6 files changed, 23 insertions, 3 deletions
diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp index 0e44b31ae3..239d4ef995 100644 --- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -20,6 +20,14 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; +// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target +// namespace. But SPARC backend uses "SP" as its namespace. +namespace llvm { +namespace Sparc { + using namespace SP; +} +} + #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR #include "SparcGenAsmWriter.inc" diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td index 7242c59059..efa7924384 100644 --- a/lib/Target/Sparc/SparcInstrAliases.td +++ b/lib/Target/Sparc/SparcInstrAliases.td @@ -140,3 +140,6 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; // mov simm13, rd -> or %g0, simm13, rd def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; + +// restore -> restore %g0, %g0, %g0 +def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll index 95f1684d68..050b76d514 100644 --- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll +++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll @@ -21,7 +21,8 @@ entry: ;SPARC64: save %sp, -128, %sp ;SPARC64: add %fp, 2047, %i0 ;SPARC64: ret -;SPARC64: restore %g0, %g0, %g0 +;SPARC64-NOT: restore %g0, %g0, %g0 +;SPARC64: restore %0 = tail call i8* @llvm.frameaddress(i32 0) ret i8* %0 diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll index 8173d6da93..60bdf06dfd 100644 --- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll +++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll @@ -141,7 +141,8 @@ entry: ;CHECK-LABEL: restore_or_imm: ;CHECK: or %o0, 20, %i0 ;CHECK: ret -;CHECK: restore %g0, %g0, %g0 +;CHECK-NOT: restore %g0, %g0, %g0 +;CHECK: restore %0 = tail call i32 @bar(i32 %a) nounwind %1 = or i32 %0, 20 ret i32 %1 @@ -174,7 +175,8 @@ define i32 @restore_sethi_large(i32 %a) { entry: ;CHECK-LABEL: restore_sethi_large: ;CHECK: sethi 4000, %i0 -;CHECK: restore %g0, %g0, %g0 +;CHECK-NOT: restore %g0, %g0, %g0 +;CHECK: restore %0 = tail call i32 @bar(i32 %a) nounwind %1 = icmp ne i32 %0, 0 %2 = select i1 %1, i32 4096000, i32 0 diff --git a/test/MC/Disassembler/Sparc/sparc.txt b/test/MC/Disassembler/Sparc/sparc.txt index 388dd68717..fefde2c703 100644 --- a/test/MC/Disassembler/Sparc/sparc.txt +++ b/test/MC/Disassembler/Sparc/sparc.txt @@ -167,3 +167,6 @@ # CHECK: fbo 4194303 0x1f 0xbf 0xff 0xff + +# CHECK: restore +0x81 0xe8 0x00 0x00 diff --git a/test/MC/Sparc/sparc-alu-instructions.s b/test/MC/Sparc/sparc-alu-instructions.s index 5531bcca7a..ef337b0032 100644 --- a/test/MC/Sparc/sparc-alu-instructions.s +++ b/test/MC/Sparc/sparc-alu-instructions.s @@ -75,3 +75,6 @@ ! CHECK: or %g0, 255, %g3 ! encoding: [0x86,0x10,0x20,0xff] mov 0xff, %g3 + + ! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00] + restore %g0, %g0, %g0 |