diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vshift_split.ll | 8 | ||||
| -rw-r--r-- | test/CodeGen/X86/vshift_split.ll | 4 |
3 files changed, 15 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f04b45dc79..7d8362c93d 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2134,8 +2134,11 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, N->getOperand(0), NegatedCount); } - assert(VT == MVT::i64 && - (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && + // We can get here for a node like i32 = ISD::SHL i32, i64 + if (VT != MVT::i64) + return SDValue(); + + assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"); // We only lower SRA, SRL of 1 here, all others use generic lowering. diff --git a/test/CodeGen/ARM/vshift_split.ll b/test/CodeGen/ARM/vshift_split.ll new file mode 100644 index 0000000000..a44db66326 --- /dev/null +++ b/test/CodeGen/ARM/vshift_split.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=-neon + +; Example that requires splitting and expanding a vector shift. +define <2 x i64> @update(<2 x i64> %val) nounwind readnone { +entry: + %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1] + ret <2 x i64> %shr +} diff --git a/test/CodeGen/X86/vshift_split.ll b/test/CodeGen/X86/vshift_split.ll index 8f485ddd9a..a1376e54cf 100644 --- a/test/CodeGen/X86/vshift_split.ll +++ b/test/CodeGen/X86/vshift_split.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | llc +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 ; Example that requires splitting and expanding a vector shift. define <2 x i64> @update(<2 x i64> %val) nounwind readnone { entry: - %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1] + %shr = lshr <2 x i64> %val, < i64 2, i64 3 > ret <2 x i64> %shr } |