diff options
| -rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/R600/fneg.ll | 26 |
2 files changed, 29 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 2a4e44f862..d74d9f89c3 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -78,6 +78,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::LOAD, MVT::f64, Promote); AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64); + setOperationAction(ISD::FNEG, MVT::v2f32, Expand); + setOperationAction(ISD::FNEG, MVT::v4f32, Expand); + setOperationAction(ISD::MUL, MVT::i64, Expand); setOperationAction(ISD::UDIV, MVT::i32, Expand); diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll new file mode 100644 index 0000000000..b95cee3676 --- /dev/null +++ b/test/CodeGen/R600/fneg.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; XXX: There is a bug in the DAGCombiner that lowers fneg to XOR, this test +; will need to be changed once it is fixed. + +; CHECK: @fneg_v2 +; CHECK: XOR_INT +; CHECK: XOR_INT +define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { +entry: + %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; CHECK: @fneg_v4 +; CHECK: XOR_INT +; CHECK: XOR_INT +; CHECK: XOR_INT +; CHECK: XOR_INT +define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { +entry: + %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} |