diff options
| -rw-r--r-- | lib/VMCore/Instructions.cpp | 8 | ||||
| -rw-r--r-- | test/Transforms/InstCombine/cast.ll | 11 |
2 files changed, 19 insertions, 0 deletions
diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp index a32cb3c871..381b85faa4 100644 --- a/lib/VMCore/Instructions.cpp +++ b/lib/VMCore/Instructions.cpp @@ -2006,6 +2006,14 @@ unsigned CastInst::isEliminableCastPair( { 99,99,99,99,99,99,99,99,99,13,99,12 }, // IntToPtr | { 5, 5, 5, 6, 6, 5, 5, 6, 6,11, 5, 1 }, // BitCast -+ }; + + // If either of the casts are a bitcast from scalar to vector, disallow the + // merging. + if ((firstOp == Instruction::BitCast && + isa<VectorType>(SrcTy) != isa<VectorType>(MidTy)) || + (secondOp == Instruction::BitCast && + isa<VectorType>(MidTy) != isa<VectorType>(DstTy))) + return 0; // Disallowed int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin] [secondOp-Instruction::CastOpsBegin]; diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll index 77fccdfa52..102d2f048f 100644 --- a/test/Transforms/InstCombine/cast.ll +++ b/test/Transforms/InstCombine/cast.ll @@ -638,3 +638,14 @@ define <4 x i32> @test62(<3 x float> %call4) nounwind { ; CHECK-NEXT: ret } +; PR7311 - Don't create invalid IR on scalar->vector cast. +define <2 x float> @test63(i64 %tmp8) nounwind { +entry: + %a = bitcast i64 %tmp8 to <2 x i32> + %vcvt.i = uitofp <2 x i32> %a to <2 x float> + ret <2 x float> %vcvt.i +; CHECK: @test63 +; CHECK: bitcast +; CHECK: uitofp +} + |