diff options
| -rw-r--r-- | lib/MC/ELFObjectWriter.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMAsmBackend.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMFixupKinds.h | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 14 | ||||
| -rw-r--r-- | utils/TableGen/EDEmitter.cpp | 1 |
7 files changed, 34 insertions, 3 deletions
diff --git a/lib/MC/ELFObjectWriter.cpp b/lib/MC/ELFObjectWriter.cpp index ac39979766..a193d165e9 100644 --- a/lib/MC/ELFObjectWriter.cpp +++ b/lib/MC/ELFObjectWriter.cpp @@ -1558,6 +1558,7 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target, case ARM::fixup_arm_thumb_bl: case ARM::fixup_arm_thumb_cb: case ARM::fixup_arm_thumb_cp: + case ARM::fixup_arm_thumb_br: assert(0 && "Unimplemented"); break; case ARM::fixup_arm_branch: Type = ELF::R_ARM_CALL; break; diff --git a/lib/Target/ARM/ARMAsmBackend.cpp b/lib/Target/ARM/ARMAsmBackend.cpp index de05472f90..536d282d0a 100644 --- a/lib/Target/ARM/ARMAsmBackend.cpp +++ b/lib/Target/ARM/ARMAsmBackend.cpp @@ -200,6 +200,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { uint32_t Binary = (Value - 4) >> 1; return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3); } + case ARM::fixup_arm_thumb_br: + // Offset by 4 and don't encode the lower bit, which is always 0. + return ((Value - 4) >> 1) & 0x7ff; case ARM::fixup_arm_thumb_bcc: // Offset by 4 and don't encode the lower bit, which is always 0. return ((Value - 4) >> 1) & 0xff; @@ -317,6 +320,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case ARM::fixup_arm_thumb_cp: return 1; + case ARM::fixup_arm_thumb_br: case ARM::fixup_arm_thumb_cb: return 2; diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index a080a4e604..dc9f52488c 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -175,6 +175,8 @@ namespace { const { return 0; } unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) + const { return 0; } unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) diff --git a/lib/Target/ARM/ARMFixupKinds.h b/lib/Target/ARM/ARMFixupKinds.h index 51bebafa9e..d21a81a0fc 100644 --- a/lib/Target/ARM/ARMFixupKinds.h +++ b/lib/Target/ARM/ARMFixupKinds.h @@ -40,6 +40,9 @@ enum Fixups { // instructions. fixup_t2_branch, + // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions. + fixup_arm_thumb_br, + // fixup_arm_thumb_blx - Fixup for Thumb BL instructions. fixup_arm_thumb_bl, diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 6c4a8fc40d..e25e9cc9d9 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -74,6 +74,10 @@ def t_imm_s4 : Operand<i32> { // Define Thumb specific addressing modes. +def t_brtarget : Operand<OtherVT> { + let EncoderMethod = "getThumbBRTargetOpValue"; +} + def t_bcctarget : Operand<i32> { let EncoderMethod = "getThumbBCCTargetOpValue"; } @@ -492,11 +496,15 @@ let isCall = 1, let isBranch = 1, isTerminator = 1, isBarrier = 1 in { let isPredicable = 1 in - def tB : T1I<(outs), (ins brtarget:$target), IIC_Br, + def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br, "b\t$target", [(br bb:$target)]>, - T1Encoding<{1,1,1,0,0,?}>; + T1Encoding<{1,1,1,0,0,?}> { + bits<11> target; + let Inst{10-0} = target; + } // Far jump + // FIXME: Encoding. This should probably be a pseudo for tBL let Defs = [LR] in def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br, "bl\t$target",[]>; diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 919070cf82..bf869f703b 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -59,6 +59,7 @@ public: { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_movt_hi16", 0, 16, 0 }, { "fixup_arm_movw_lo16", 0, 16, 0 }, @@ -101,6 +102,10 @@ public: uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; + /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. + uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl<MCFixup> &Fixups) const; + /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; @@ -457,10 +462,17 @@ getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups); } +/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. +uint32_t ARMMCCodeEmitter:: +getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl<MCFixup> &Fixups) const { + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups); +} + /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. uint32_t ARMMCCodeEmitter:: getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl<MCFixup> &Fixups) const { + SmallVectorImpl<MCFixup> &Fixups) const { return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups); } diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index b17390de2b..e114b0d45a 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -587,6 +587,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, IMM("neon_vcvt_imm32"); MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? + MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ? MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ? MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ? MISC("bltarget", "kOperandTypeARMBranchTarget"); // ? |