diff options
| -rw-r--r-- | lib/Target/Alpha/AlphaTargetMachine.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index f5bd484b0c..3ee13002a3 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -29,9 +29,6 @@ namespace { } namespace llvm { - cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha", - cl::desc("Enable LSR for Alpha (beta option!)"), - cl::Hidden); cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha", cl::desc("Enable DAG ISEL for Alpha (beta option!)"), cl::Hidden); @@ -81,10 +78,7 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM, bool Fast) { if (FileType != TargetMachine::AssemblyFile) return true; - if (EnableAlphaLSR) { - PM.add(createLoopStrengthReducePass()); - PM.add(createCFGSimplificationPass()); - } + PM.add(createLoopStrengthReducePass()); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -98,6 +92,8 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); + PM.add(createCFGSimplificationPass()); + if (EnableAlphaDAG) PM.add(createAlphaISelDag(*this)); else |