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-rw-r--r--lib/Target/AArch64/AArch64TargetMachine.cpp2
-rw-r--r--lib/Target/ARM/ARMTargetMachine.cpp2
-rw-r--r--lib/Target/Hexagon/HexagonTargetMachine.cpp2
-rw-r--r--lib/Target/MSP430/MSP430TargetMachine.cpp2
-rw-r--r--lib/Target/Mips/MipsTargetMachine.cpp4
-rw-r--r--lib/Target/NVPTX/NVPTXTargetMachine.cpp4
-rw-r--r--lib/Target/PowerPC/PPCTargetMachine.cpp2
-rw-r--r--lib/Target/R600/AMDGPUTargetMachine.cpp6
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.cpp6
-rw-r--r--lib/Target/X86/X86TargetMachine.cpp6
-rw-r--r--lib/Target/XCore/XCoreTargetMachine.cpp2
11 files changed, 19 insertions, 19 deletions
diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp
index bfa496075b..2617b2a416 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -34,7 +34,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
InstrInfo(Subtarget),
- DL("e-i64:64:64-i128:128:128-s:32:32-n32:64-S128"),
+ DL("e-i64:64-i128:128-s:32-n32:64-S128"),
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index d5cde41b11..0bc0fa2a54 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -77,7 +77,7 @@ static std::string computeDataLayout(ARMSubtarget &ST) {
if (ST.isAPCS_ABI())
Ret += "-f64:32:64";
else
- Ret += "-i64:64:64";
+ Ret += "-i64:64";
// On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
// align to 32.
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index ba733689da..2be0a7ab65 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -71,7 +71,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
- DL("e-p:32:32:32-i64:64:64-i1:32:32-a:0-n32") ,
+ DL("e-p:32:32-i64:64-i1:32-a:0-n32") ,
Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget),
diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp
index b27486d21e..d9c6ba0921 100644
--- a/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
// FIXME: Check DataLayout string.
- DL("e-p:16:16:16-i32:16:32-n8:16"),
+ DL("e-p:16:16-i32:16:32-n8:16"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index 30762c6a72..6cf6ae6684 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -56,11 +56,11 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
// Pointers are 32 bit on some ABIs.
if (!ST.isABI_N64())
- Ret += "-p:32:32:32";
+ Ret += "-p:32:32";
// 8 and 16 bit integers only need no have natural alignment, but try to
// align them to 32 bits. 64 bit integers have natural alignment.
- Ret += "-i8:8:32-i16:16:32-i64:64:64";
+ Ret += "-i8:8:32-i16:16:32-i64:64";
// 32 bit registers are always available and the stack is at least 64 bit
// aligned. On N64 64 bit registers are also available and the stack is
diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 6cfd7e15e9..2c93abec6e 100644
--- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -67,9 +67,9 @@ static std::string computeDataLayout(const NVPTXSubtarget &ST) {
std::string Ret = "e";
if (!ST.is64Bit())
- Ret += "-p:32:32:32";
+ Ret += "-p:32:32";
- Ret += "-i64:64:64-v16:16:16-v32:32:32-n16:32:64";
+ Ret += "-i64:64-v16:16-v32:32-n16:32:64";
return Ret;
}
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 25badb1d0b..17799cb829 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -44,7 +44,7 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
- Ret += "-i64:64:64";
+ Ret += "-i64:64";
// Set support for 128 floats depending on the ABI.
if (!ST.isPPC64() || !ST.isSVR4ABI())
diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp
index 48ea7c84bf..5d3d932a99 100644
--- a/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -51,13 +51,13 @@ SchedCustomRegistry("r600", "Run R600's custom scheduler",
static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
std::string DataLayout = std::string(
- "e-i64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v96:128:128"
- "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+ "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
+ "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048"
"-n32:64"
);
if (!ST.is64bit())
- DataLayout.append("-p:32:32:32");
+ DataLayout.append("-p:32:32");
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
DataLayout.append("-p3:32:32:32");
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 7324e99af9..172bb66b7c 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -29,17 +29,17 @@ static std::string computeDataLayout(const SparcSubtarget &ST) {
// Some ABIs have 32bit pointers.
if (!ST.is64Bit())
- Ret += "-p:32:32:32";
+ Ret += "-p:32:32";
// Alignments for 64 bit integers.
- Ret += "-i64:64:64";
+ Ret += "-i64:64";
// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
if (ST.is64Bit())
Ret += "-n32:64";
else
- Ret += "-f128:64:64-n32";
+ Ret += "-f128:64-n32";
return Ret;
}
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 4675a4ec03..2165aefab5 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -45,15 +45,15 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
- Ret += "-i64:64:64";
+ Ret += "-i64:64";
else
Ret += "-f64:32:64";
// Some ABIs align long double to 128 bits, others to 32.
if (ST.is64Bit() || ST.isTargetDarwin())
- Ret += "-f80:128:128";
+ Ret += "-f80:128";
else
- Ret += "-f80:32:32";
+ Ret += "-f80:32";
// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
if (ST.is64Bit())
diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp
index 834d0a52fd..c01d5e9b5c 100644
--- a/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -27,7 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
- DL("e-p:32:32:32-a:0:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32:32-n32"),
+ DL("e-p:32:32-a:0:32-f64:32-i1:8:32-i8:8:32-i16:16:32-i64:32-n32"),
InstrInfo(),
FrameLowering(Subtarget),
TLInfo(*this),
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 23:16:53 +0000