diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll | 19 |
2 files changed, 21 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 3e65606c43..84cf8f6a57 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1061,7 +1061,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, if (N.getOpcode() == ISD::ADD) { short imm = 0; if (isIntS16Immediate(N.getOperand(1), imm)) { - Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); + Disp = DAG.getTargetConstant(imm, N.getValueType()); if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); } else { @@ -1093,7 +1093,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, // If all of the bits are known zero on the LHS or RHS, the add won't // carry. Base = N.getOperand(0); - Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); + Disp = DAG.getTargetConstant(imm, N.getValueType()); return true; } } diff --git a/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll b/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll new file mode 100644 index 0000000000..b75337d796 --- /dev/null +++ b/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i8* @test(i8* %base, i8 %val) { +entry: + %arrayidx = getelementptr inbounds i8* %base, i32 -1 + store i8 %val, i8* %arrayidx, align 1 + %arrayidx2 = getelementptr inbounds i8* %base, i32 1 + store i8 %val, i8* %arrayidx2, align 1 + ret i8* %arrayidx +} +; CHECK: @test +; CHECK: %entry +; CHECK-NEXT: stbu 4, -1(3) +; CHECK-NEXT: stb 4, 2(3) +; CHECK-NEXT: blr + |