diff options
| -rw-r--r-- | lib/Target/NVPTX/NVPTXISelLowering.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/NVPTX/add-128bit.ll | 19 |
2 files changed, 22 insertions, 0 deletions
diff --git a/lib/Target/NVPTX/NVPTXISelLowering.cpp b/lib/Target/NVPTX/NVPTXISelLowering.cpp index f2578584bc..04fb784b85 100644 --- a/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -204,6 +204,9 @@ NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM) // TRAP can be lowered to PTX trap setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::ADDC, MVT::i64, Expand); + setOperationAction(ISD::ADDE, MVT::i64, Expand); + // Register custom handling for vector loads/stores for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { diff --git a/test/CodeGen/NVPTX/add-128bit.ll b/test/CodeGen/NVPTX/add-128bit.ll new file mode 100644 index 0000000000..29e3cdffae --- /dev/null +++ b/test/CodeGen/NVPTX/add-128bit.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" + + + +define void @foo(i64 %a, i64 %add, i128* %retptr) { +; CHECK: add.s64 +; CHECK: setp.lt.u64 +; CHECK: setp.lt.u64 +; CHECK: selp.b64 +; CHECK: selp.b64 +; CHECK: add.s64 + %t1 = sext i64 %a to i128 + %add2 = zext i64 %add to i128 + %val = add i128 %t1, %add2 + store i128 %val, i128* %retptr + ret void +} |