diff options
Diffstat (limited to 'include/llvm/Target/TargetInstrInfo.h')
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 57 |
1 files changed, 4 insertions, 53 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 7144fe092e..d95e4e8acd 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -45,55 +45,6 @@ public: TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); virtual ~TargetInstrInfo(); - // Invariant opcodes: All instruction sets have these as their low opcodes. - enum { - PHI = 0, - INLINEASM = 1, - DBG_LABEL = 2, - EH_LABEL = 3, - GC_LABEL = 4, - - /// KILL - This instruction is a noop that is used only to adjust the liveness - /// of registers. This can be useful when dealing with sub-registers. - KILL = 5, - - /// EXTRACT_SUBREG - This instruction takes two operands: a register - /// that has subregisters, and a subregister index. It returns the - /// extracted subregister value. This is commonly used to implement - /// truncation operations on target architectures which support it. - EXTRACT_SUBREG = 6, - - /// INSERT_SUBREG - This instruction takes three operands: a register - /// that has subregisters, a register providing an insert value, and a - /// subregister index. It returns the value of the first register with - /// the value of the second register inserted. The first register is - /// often defined by an IMPLICIT_DEF, as is commonly used to implement - /// anyext operations on target architectures which support it. - INSERT_SUBREG = 7, - - /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. - IMPLICIT_DEF = 8, - - /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except - /// that the first operand is an immediate integer constant. This constant - /// is often zero, as is commonly used to implement zext operations on - /// target architectures which support it, such as with x86-64 (with - /// zext from i32 to i64 via implicit zero-extension). - SUBREG_TO_REG = 9, - - /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain - /// register-to-register copy into a specific register class. This is only - /// used between instruction selection and MachineInstr creation, before - /// virtual registers have been created for all the instructions, and it's - /// only needed in cases where the register classes implied by the - /// instructions are insufficient. The actual MachineInstrs to perform - /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. - COPY_TO_REGCLASS = 10, - - // DEBUG_VALUE - a mapping of the llvm.dbg.value intrinsic - DEBUG_VALUE = 11 - }; - unsigned getNumOpcodes() const { return NumOpcodes; } /// get - Return the machine instruction descriptor that corresponds to the @@ -109,7 +60,7 @@ public: /// that aren't always available. bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA = 0) const { - return MI->getOpcode() == IMPLICIT_DEF || + return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || (MI->getDesc().isRematerializable() && (isReallyTriviallyReMaterializable(MI, AA) || isReallyTriviallyReMaterializableGeneric(MI, AA))); @@ -167,12 +118,12 @@ public: SrcReg == DstReg) return true; - if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && + if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG && MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) return true; - if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || - MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && + if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || + MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) return true; return false; |