1 files changed, 16 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 5afcd80a28..2e4956f16d 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -218,6 +218,10 @@ public:
   /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
   bool isPow2DivCheap() const { return Pow2DivIsCheap; }
 
+  /// Return true if Div never traps, returns 0 when div by 0 and return TMin,
+  /// when sdiv TMin by -1.
+  bool isDivWellDefined() const { return DivIsWellDefined; }
+
   /// Return true if Flow Control is an expensive operation that should be
   /// avoided.
   bool isJumpExpensive() const { return JumpIsExpensive; }
@@ -1026,6 +1030,13 @@ protected:
   /// signed divide by power of two, and let the target handle it.
   void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
 
+  /// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem
+  /// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is
+  /// SignedMinValue and RHS is -1.
+  void setDivIsWellDefined (bool isWellDefined = true) {
+    DivIsWellDefined = isWellDefined;
+  }
+
   /// Add the specified register class as an available regclass for the
   /// specified value type. This indicates the selector can handle values of
   /// that class natively.
@@ -1441,6 +1452,11 @@ private:
   /// signed divide by power of two, and let the target handle it.
   bool Pow2DivIsCheap;
 
+  /// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem
+  /// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is
+  /// SignedMinValue and RHS is -1.
+  bool DivIsWellDefined;
+
   /// Tells the code generator that it shouldn't generate extra flow control
   /// instructions and should attempt to combine flow control instructions via
   /// predication.