diff options
Diffstat (limited to 'include/llvm')
-rw-r--r-- | include/llvm/CodeGen/ISDOpcodes.h | 3 | ||||
-rw-r--r-- | include/llvm/Intrinsics.td | 3 | ||||
-rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 4 |
3 files changed, 6 insertions, 4 deletions
diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index e765cadf4d..498614e7fd 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -580,7 +580,8 @@ namespace ISD { // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are // their first operand. The other operands are the address to prefetch, - // read / write specifier, and locality specifier. + // read / write specifier, locality specifier and instruction / data cache + // specifier. PREFETCH, // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td index d8f249a2c0..c1fbce4e05 100644 --- a/include/llvm/Intrinsics.td +++ b/include/llvm/Intrinsics.td @@ -211,7 +211,8 @@ def int_stackrestore : Intrinsic<[], [llvm_ptr_ty]>, // however it does conveniently prevent the prefetch from being reordered // with respect to nearby accesses to the same memory. def int_prefetch : Intrinsic<[], - [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, + llvm_i32_ty], [IntrReadWriteArgMem, NoCapture<0>]>; def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>; diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 672117f144..285b8b1abd 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -197,8 +197,8 @@ def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> ]>; -def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch - SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> +def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch + SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> ]>; def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier |