diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/CodeGen/MachineMemOperand.h | 5 | ||||
-rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 6 | ||||
-rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 9 |
3 files changed, 12 insertions, 8 deletions
diff --git a/include/llvm/CodeGen/MachineMemOperand.h b/include/llvm/CodeGen/MachineMemOperand.h index 768ce47f8b..c01597ea67 100644 --- a/include/llvm/CodeGen/MachineMemOperand.h +++ b/include/llvm/CodeGen/MachineMemOperand.h @@ -95,8 +95,10 @@ public: MOVolatile = 4, /// The memory access is non-temporal. MONonTemporal = 8, + /// The memory access is invariant. + MOInvariant = 16, // This is the number of bits we need to represent flags. - MOMaxBits = 4 + MOMaxBits = 5 }; /// MachineMemOperand - Construct an MachineMemOperand object with the @@ -141,6 +143,7 @@ public: bool isStore() const { return Flags & MOStore; } bool isVolatile() const { return Flags & MOVolatile; } bool isNonTemporal() const { return Flags & MONonTemporal; } + bool isInvariant() const { return Flags & MOInvariant; } /// refineAlignment - Update this MachineMemOperand to reflect the alignment /// of MMO, if it has a greater alignment. This must only be used when the diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 132983c504..e4de462e00 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -650,7 +650,7 @@ public: /// SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, - bool isNonTemporal, unsigned Alignment, + bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo = 0); SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, @@ -663,8 +663,8 @@ public: EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, - bool isVolatile, bool isNonTemporal, unsigned Alignment, - const MDNode *TBAAInfo = 0); + bool isVolatile, bool isNonTemporal, bool isInvariant, + unsigned Alignment, const MDNode *TBAAInfo = 0); SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 6c7be69b4d..285f2fc373 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -917,12 +917,13 @@ public: // with MachineMemOperand information. bool isVolatile() const { return (SubclassData >> 5) & 1; } bool isNonTemporal() const { return (SubclassData >> 6) & 1; } + bool isInvariant() const { return (SubclassData >> 7) & 1; } AtomicOrdering getOrdering() const { - return AtomicOrdering((SubclassData >> 7) & 15); + return AtomicOrdering((SubclassData >> 8) & 15); } SynchronizationScope getSynchScope() const { - return SynchronizationScope((SubclassData >> 11) & 1); + return SynchronizationScope((SubclassData >> 12) & 1); } /// Returns the SrcValue and offset that describes the location of the access @@ -993,8 +994,8 @@ class AtomicSDNode : public MemSDNode { "Ordering may not require more than 4 bits!"); assert((SynchScope & 1) == SynchScope && "SynchScope may not require more than 1 bit!"); - SubclassData |= Ordering << 7; - SubclassData |= SynchScope << 11; + SubclassData |= Ordering << 8; + SubclassData |= SynchScope << 12; assert(getOrdering() == Ordering && "Ordering encoding error!"); assert(getSynchScope() == SynchScope && "Synch-scope encoding error!"); |