diff options
Diffstat (limited to 'lib/Target/AArch64')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrInfo.td | 7 | ||||
| -rw-r--r-- | lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h | 4 |
3 files changed, 17 insertions, 3 deletions
diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index 7d7a641a2e..c4e43e1a8f 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -1587,6 +1587,7 @@ def inv_cond_code_op_asmoperand : AsmOperandClass { def inv_cond_code_op : Operand<i32> { let ParserMatchClass = inv_cond_code_op_asmoperand; + let PrintMethod = "printInverseCondCodeOperand"; } // Having a separate operand for the selectable use-case is debatable, but gives @@ -3864,15 +3865,15 @@ let Defs = [NZCV] in { Sched<[WriteALU, ReadALU]>; } - def : InstAlias<"tst $Rn, $Imm", (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>; def : InstAlias<"tst $Rn, $Imm", (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>; +// FIXME: these sometimes are canonical. def : InstAlias<"mov $Rd, $Imm", - (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>; + (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm), 0>; def : InstAlias<"mov $Rd, $Imm", - (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>; + (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm), 0>; //===----------------------------------------------------------------------===// // Logical (shifted register) instructions diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp index 032120771a..d9571238a0 100644 --- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -210,6 +210,15 @@ AArch64InstPrinter::printCondCodeOperand(const MCInst *MI, unsigned OpNum, O << A64CondCodeToString(static_cast<A64CC::CondCodes>(MO.getImm())); } +void +AArch64InstPrinter::printInverseCondCodeOperand(const MCInst *MI, + unsigned OpNum, + raw_ostream &O) { + A64CC::CondCodes CC = + static_cast<A64CC::CondCodes>(MI->getOperand(OpNum).getImm()); + O << A64CondCodeToString(A64InvertCondCode(CC)); +} + template <unsigned field_width, unsigned scale> void AArch64InstPrinter::printLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h index a0319a95ef..7432755dd8 100644 --- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h +++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h @@ -31,6 +31,8 @@ public: // Autogenerated by tblgen void printInstruction(const MCInst *MI, raw_ostream &O); bool printAliasInstr(const MCInst *MI, raw_ostream &O); + void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); static const char *getInstructionName(unsigned Opcode); @@ -62,6 +64,8 @@ public: void printCondCodeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printInverseCondCodeOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); void printCRxOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); |