1 files changed, 0 insertions, 51 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index c130b2eede..f7c8a9c2dc 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1208,57 +1208,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
       ExpandLaneOp(MBBI);
       return true;
 
-    case ARM::VSETLNi8Q:
-    case ARM::VSETLNi16Q: {
-      // Expand VSETLNs acting on a Q register to equivalent VSETLNs acting
-      // on the respective D register.
-
-      unsigned QReg  = MI.getOperand(1).getReg();
-      unsigned QLane = MI.getOperand(3).getImm();
-
-      unsigned NewOpcode, DLane, DSubReg;
-      switch (Opcode) {
-      default: llvm_unreachable("Invalid opcode!");
-      case ARM::VSETLNi8Q:
-        // 4 possible 8-bit lanes per DPR:
-        NewOpcode = ARM::VSETLNi8;
-        DLane = QLane % 8;
-        DSubReg  = (QLane / 8) ? ARM::dsub_1 : ARM::dsub_0;
-        break;
-      case ARM::VSETLNi16Q:
-        // 4 possible 16-bit lanes per DPR.
-        NewOpcode = ARM::VSETLNi16;
-        DLane = QLane % 4;
-        DSubReg  = (QLane / 4) ? ARM::dsub_1 : ARM::dsub_0;
-        break;
-      }
-
-      MachineInstrBuilder MIB =
-        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpcode));
-
-      unsigned DReg = TRI->getSubReg(QReg, DSubReg);
-
-      MIB.addReg(DReg, RegState::Define); // Output DPR
-      MIB.addReg(DReg);                   // Input DPR
-      MIB.addOperand(MI.getOperand(2));   // Input GPR
-      MIB.addImm(DLane);                  // Lane
-
-      // Add the predicate operands.
-      MIB.addOperand(MI.getOperand(4));
-      MIB.addOperand(MI.getOperand(5));
-
-      if (MI.getOperand(1).isKill()) // Add an implicit kill for the Q register.
-        MIB->addRegisterKilled(QReg, TRI, true);
-      // And an implicit def of the output register (which should always be the
-      // same as the input register).
-      MIB->addRegisterDefined(QReg, TRI);
-
-      TransferImpOps(MI, MIB, MIB);
-
-      MI.eraseFromParent();
-      return true;
-    }
-
     case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
     case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
     case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;