5 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 8933a02701..1458e33c62 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -276,7 +276,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
   if (TII.isPredicable(MI) || isARMNEONPred(MI))
     AddDefaultPred(MIB);
 
-  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
+  // Do we optionally set a predicate?  Preds is size > 0 if the predicate
   // defines CPSR. All other OptionalDefines in ARM are the CCR register.
   bool CPSR = false;
   if (DefinesOptionalPredicate(MI, &CPSR)) {
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 1eea0cc61d..e9f0c8ad5a 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -2117,7 +2117,7 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
   if (N->getOpcode() == ISD::AND) {
     if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
 
-      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
+      // The immediate is a mask of the low bits if imm & (imm+1) == 0
       if (And_imm & (And_imm + 1))
         return NULL;
 
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index f8455a4b0e..33c48350a7 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -727,7 +727,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
       !Subtarget->isThumb1Only()) {
     // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
-    // iff target supports vfp2.
+    // if target supports vfp2.
     setOperationAction(ISD::BITCAST, MVT::i64, Custom);
     setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
   }
@@ -7692,12 +7692,12 @@ static SDValue PerformORCombine(SDNode *N,
 
   DebugLoc DL = N->getDebugLoc();
   // 1) or (and A, mask), val => ARMbfi A, val, mask
-  //      iff (val & mask) == val
+  //      if (val & mask) == val
   //
   // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
-  //  2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
+  //  2a) if isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
   //          && mask == ~mask2
-  //  2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
+  //  2b) if isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
   //          && ~mask == mask2
   //  (i.e., copy a bitfield value into another bitfield of the same width)
 
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index e171f8b092..ca3d6d7dac 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -698,7 +698,7 @@ def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
 }
 
 // Writeback version is just a pseudo, as there's no encoding difference.
-// Writeback happens iff the base register is not in the destination register
+// Writeback happens if the base register is not in the destination register
 // list.
 def tLDMIA_UPD :
     InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index aa5ba46ab2..a16931ebd8 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5316,7 +5316,7 @@ validateInstruction(MCInst &Inst,
     // instruction. We'll make the transformation in processInstruction()
     // if necessary.
     //
-    // Thumb LDM instructions are writeback iff the base register is not
+    // Thumb LDM instructions are writeback if the base register is not
     // in the register list.
     unsigned Rn = Inst.getOperand(0).getReg();
     bool hasWritebackToken =
@@ -7023,7 +7023,7 @@ processInstruction(MCInst &Inst,
     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
     break;
   case ARM::tADDi8:
-    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
+    // If the immediate is in the range 0-7, we want tADDi3 if Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
     // to encoding T1 if <Rd> is omitted."
@@ -7033,7 +7033,7 @@ processInstruction(MCInst &Inst,
     }
     break;
   case ARM::tSUBi8:
-    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
+    // If the immediate is in the range 0-7, we want tADDi3 if Rd was
     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
     // to encoding T1 if <Rd> is omitted."