diff options
Diffstat (limited to 'lib/Target/Hexagon')
| -rw-r--r-- | lib/Target/Hexagon/HexagonHardwareLoops.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonImmediates.td | 2 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonNewValueJump.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp | 2 |
6 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index c31cf43a11..1357cc54e6 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -491,7 +491,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) { TII->get(Hexagon::NEG), CountReg).addReg(CountReg1); } - // Add the Loop instruction to the begining of the loop. + // Add the Loop instruction to the beginning of the loop. BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(), TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg); } else { diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 1fa1d10009..7505617221 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -508,7 +508,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Build a sequence of copy-to-reg nodes chained together with token // chain and flag operands which copy the outgoing args into registers. - // The InFlag in necessary since all emited instructions must be + // The InFlag in necessary since all emitted instructions must be // stuck together. SDValue InFlag; if (!isTailCall) { @@ -528,7 +528,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // than necessary, because it means that each store effectively depends // on every argument instead of just those arguments it would clobber. // - // Do not flag preceeding copytoreg stuff together with the following stuff. + // Do not flag preceding copytoreg stuff together with the following stuff. InFlag = SDValue(); for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, diff --git a/lib/Target/Hexagon/HexagonImmediates.td b/lib/Target/Hexagon/HexagonImmediates.td index e78bb790ae..18692c4dcc 100644 --- a/lib/Target/Hexagon/HexagonImmediates.td +++ b/lib/Target/Hexagon/HexagonImmediates.td @@ -371,7 +371,7 @@ def s4_3ImmPred : PatLeaf<(i32 imm), [{ def u64ImmPred : PatLeaf<(i64 imm), [{ // immS16 predicate - True if the immediate fits in a 16-bit sign extended // field. - // Adding "N ||" to supress gcc unused warning. + // Adding "N ||" to suppress gcc unused warning. return (N || true); }]>; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 8eb6868fc7..16448004a8 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -3029,7 +3029,7 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)), (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))))>; -// We want to prevent emiting pnot's as much as possible. +// We want to prevent emitting pnot's as much as possible. // Map brcond with an unsupported setcc to a JMP_cNot. def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))), bb:$offset), diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index 051fc1971e..c93b56debe 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -9,9 +9,9 @@ // // This implements NewValueJump pass in Hexagon. // Ideally, we should merge this as a Peephole pass prior to register -// allocation, but becuase we have a spill in between the feeder and new value +// allocation, but because we have a spill in between the feeder and new value // jump instructions, we are forced to write after register allocation. -// Having said that, we should re-attempt to pull this ealier at some piont +// Having said that, we should re-attempt to pull this earlier at some point // in future. // The basic approach looks for sequence of predicated jump, compare instruciton diff --git a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp index 66a00e12dd..2468f0b86f 100644 --- a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp +++ b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp @@ -1,4 +1,4 @@ -//===- HexagonRemoveExtendArgs.cpp - Remove unecessary argument sign extends =// +//===- HexagonRemoveExtendArgs.cpp - Remove unnecessary argument sign extends // // // The LLVM Compiler Infrastructure // |