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-rw-r--r--lib/Target/SparcV9/InstrSched/InstrScheduling.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 6e6d14c7c8..edf84d4cad 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -17,6 +17,7 @@
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" // FIXME: Remove when AnalysisUsage sets can be symbolic!
#include "llvm/Target/TargetMachine.h"
#include "llvm/BasicBlock.h"
+#include "llvm/Instruction.h"
#include "SchedPriorities.h"
#include <ext/hash_set>
#include <algorithm>
@@ -1287,14 +1288,11 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
SchedGraph *graph)
{
const MachineInstrInfo& mii = S.getInstrInfo();
- const TerminatorInst *termInstr = bb->getTerminator();
+ const Instruction *termInstr = (Instruction*)bb->getTerminator();
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
- assert(termInstr->getOpcode() != Instruction::Call
- && "Call used as terminator?");
-
if (termInstr->getOpcode() != Instruction::Ret)
{
// To find instructions that need delay slots without searching the full