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Diffstat (limited to 'lib/Target/TargetRegisterInfo.cpp')
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp new file mode 100644 index 0000000000..11f1b3d070 --- /dev/null +++ b/lib/Target/TargetRegisterInfo.cpp @@ -0,0 +1,90 @@ +//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TargetRegisterInfo interface. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/ADT/BitVector.h" + +using namespace llvm; + +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, + regclass_iterator RCB, regclass_iterator RCE, + int CFSO, int CFDO) + : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { + assert(NumRegs < FirstVirtualRegister && + "Target has too many physical registers!"); + + CallFrameSetupOpcode = CFSO; + CallFrameDestroyOpcode = CFDO; +} + +TargetRegisterInfo::~TargetRegisterInfo() {} + +/// getPhysicalRegisterRegClass - Returns the Register Class of a physical +/// register. +const TargetRegisterClass * +TargetRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, + unsigned reg) const { + assert(isPhysicalRegister(reg) && "reg must be a physical register"); + // Pick the register class of the right type that contains this physreg. + for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) + if ((*I)->hasType(VT) && (*I)->contains(reg)) + return *I; + assert(false && "Couldn't find the register class"); + return 0; +} + + +/// getAllocatableSetForRC - Toggle the bits that represent allocatable +/// registers for the specific register class. +static void getAllocatableSetForRC(MachineFunction &MF, + const TargetRegisterClass *RC, BitVector &R){ + for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), + E = RC->allocation_order_end(MF); I != E; ++I) + R.set(*I); +} + +BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC) const { + BitVector Allocatable(NumRegs); + if (RC) { + getAllocatableSetForRC(MF, RC, Allocatable); + return Allocatable; + } + + for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), + E = regclass_end(); I != E; ++I) + getAllocatableSetForRC(MF, *I, Allocatable); + return Allocatable; +} + +/// getFrameIndexOffset - Returns the displacement from the frame register to +/// the stack frame of the specified index. This is the default implementation +/// which is likely incorrect for the target. +int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { + const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + return MFI->getObjectOffset(FI) + MFI->getStackSize() - + TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment(); +} + +/// getInitialFrameState - Returns a list of machine moves that are assumed +/// on entry to a function. +void +TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const { + // Default is to do nothing. +} + |