diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM64/ARM64InstrFormats.td | 10 | ||||
| -rw-r--r-- | lib/Target/ARM64/ARM64InstrInfo.td | 12 |
2 files changed, 7 insertions, 15 deletions
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index edbdfec7e5..875f0aebde 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -5595,13 +5595,11 @@ class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype, : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov", [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>; -// FIXME: these aliases should be canonical, but TableGen can't handle the -// alternate syntaxes. class SIMDMovAlias<string asm, string size, Instruction inst, RegisterClass regtype, Operand idxtype> : InstAlias<asm#"{\t$dst, $src"#size#"$idx" # "|" # size # "\t$dst, $src$idx}", - (inst regtype:$dst, V128:$src, idxtype:$idx), 0>; + (inst regtype:$dst, V128:$src, idxtype:$idx)>; multiclass SMov { def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> { @@ -5685,18 +5683,16 @@ class SIMDInsFromElement<string size, ValueType vectype, (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)), idxtype:$idx))]>; -// FIXME: the MOVs should be canonical, but TableGen's alias printing can't cope -// with syntax variants. class SIMDInsMainMovAlias<string size, Instruction inst, RegisterClass regtype, Operand idxtype> : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # "|" # size #"\t$dst$idx, $src}", - (inst V128:$dst, idxtype:$idx, regtype:$src), 0>; + (inst V128:$dst, idxtype:$idx, regtype:$src)>; class SIMDInsElementMovAlias<string size, Instruction inst, Operand idxtype> : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" # # "|" # size #" $dst$idx, $src$idx2}", - (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2), 0>; + (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>; multiclass SIMDIns { diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td index 268ba4e44d..5d46ac6125 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.td +++ b/lib/Target/ARM64/ARM64InstrInfo.td @@ -2315,10 +2315,10 @@ defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", UnOpFrag<(sub immAllZerosV, node:$LHS)> >; defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; // Aliases for MVN -> NOT. -def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>; -def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>; -def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>; -def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>; +def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", + (NOTv8i8 V64:$Vd, V64:$Vn)>; +def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", + (NOTv16i8 V128:$Vd, V128:$Vn)>; def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>; def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>; @@ -3733,8 +3733,6 @@ def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>; // EDIT per word & halfword: 2s, 4h, 4s, & 8h defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">; -// FIXME: these should be canonical but the TableGen alias printer can't cope -// with syntax variants. def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; @@ -3775,8 +3773,6 @@ def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255, // EDIT per word & halfword: 2s, 4h, 4s, & 8h defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; -// FIXME: these should be canonical, but TableGen can't do aliases & syntax -// variants together. def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; |