summaryrefslogtreecommitdiff
path: root/lib/Target
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/AArch64/AArch64FrameLowering.cpp10
-rw-r--r--lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp2
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp6
-rw-r--r--lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp8
-rw-r--r--lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp62
-rw-r--r--lib/Target/Mangler.cpp30
-rw-r--r--lib/Target/Mips/AsmParser/MipsAsmParser.cpp2
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp2
-rw-r--r--lib/Target/Mips/Mips16FrameLowering.cpp8
-rw-r--r--lib/Target/Mips/MipsSEFrameLowering.cpp12
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp6
-rw-r--r--lib/Target/PowerPC/PPCFrameLowering.cpp12
-rw-r--r--lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp2
-rw-r--r--lib/Target/SystemZ/SystemZFrameLowering.cpp8
-rw-r--r--lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp2
-rw-r--r--lib/Target/X86/X86FrameLowering.cpp4
16 files changed, 88 insertions, 88 deletions
diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp
index 8b907b2fb3..d5717650f6 100644
--- a/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -54,7 +54,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
MachineModuleInfo &MMI = MF.getMMI();
- const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
bool NeedsFrameMoves = MMI.hasDebugInfo()
|| MF.getFunction()->needsUnwindTableEntry();
@@ -97,7 +97,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
.addSym(SPLabel);
MachineLocation Dst(MachineLocation::VirtualFP);
- unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
+ unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
MMI.addFrameInst(
MCCFIInstruction::createDefCfa(SPLabel, Reg, -NumInitialBytes));
}
@@ -132,7 +132,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
.addSym(FPLabel);
- unsigned Reg = MRI.getDwarfRegNum(AArch64::X29, true);
+ unsigned Reg = MRI->getDwarfRegNum(AArch64::X29, true);
unsigned Offset = MFI->getObjectOffset(X29FrameIdx);
MMI.addFrameInst(MCCFIInstruction::createDefCfa(FPLabel, Reg, Offset));
}
@@ -165,7 +165,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
.addSym(CSLabel);
MachineLocation Dst(MachineLocation::VirtualFP);
- unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
+ unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
unsigned Offset = NumResidualBytes + NumInitialBytes;
MMI.addFrameInst(MCCFIInstruction::createDefCfa(CSLabel, Reg, -Offset));
}
@@ -183,7 +183,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
E = CSI.end(); I != E; ++I) {
unsigned Offset = MFI->getObjectOffset(I->getFrameIdx());
- unsigned Reg = MRI.getDwarfRegNum(I->getReg(), true);
+ unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, Reg, Offset));
}
}
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index a5c591eee8..8cf374feca 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -346,7 +346,7 @@ AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg()) {
- return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
+ return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
}
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index c59ca64c11..e315d16574 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -277,7 +277,7 @@ public:
MCAsmParserExtension::Initialize(_Parser);
// Cache the MCRegisterInfo.
- MRI = &getContext().getRegisterInfo();
+ MRI = getContext().getRegisterInfo();
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
@@ -7851,8 +7851,8 @@ bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
/// parseDirectiveThumbFunc
/// ::= .thumbfunc symbol_name
bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
- const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
- bool isMachO = MAI.hasSubsectionsViaSymbols();
+ const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
+ bool isMachO = MAI->hasSubsectionsViaSymbols();
StringRef Name;
bool needFuncName = true;
diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index 679d3c4a85..dc3d945656 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -380,10 +380,10 @@ void ARMELFStreamer::FlushPendingOffset() {
void ARMELFStreamer::FlushUnwindOpcodes(bool AllowCompactModel0) {
// Emit the unwind opcode to restore $sp.
if (UsedFP) {
- const MCRegisterInfo &MRI = getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = getContext().getRegisterInfo();
int64_t LastRegSaveSPOffset = SPOffset - PendingOffset;
UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset);
- UnwindOpAsm.EmitSetSP(MRI.getEncodingValue(FPReg));
+ UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg));
} else {
FlushPendingOffset();
}
@@ -458,9 +458,9 @@ void ARMELFStreamer::EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
// Collect the registers in the register list
unsigned Count = 0;
uint32_t Mask = 0;
- const MCRegisterInfo &MRI = getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = getContext().getRegisterInfo();
for (size_t i = 0; i < RegList.size(); ++i) {
- unsigned Reg = MRI.getEncodingValue(RegList[i]);
+ unsigned Reg = MRI->getEncodingValue(RegList[i]);
assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
unsigned Bit = (1u << Reg);
if ((Mask & Bit) == 0) {
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 2aa1010217..f324bc2e37 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -407,7 +407,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg()) {
unsigned Reg = MO.getReg();
- unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
+ unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
// Q registers are encoded as 2x their register number.
switch (Reg) {
@@ -436,7 +436,7 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
- Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
int32_t SImm = MO1.getImm();
bool isAdd = true;
@@ -724,8 +724,8 @@ getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
// {2-0} = Rn
const MCOperand &MO1 = MI.getOperand(OpIdx);
const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
- unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
- unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
+ unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
return (Rm << 3) | Rn;
}
@@ -741,7 +741,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
+ Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
Imm12 = 0;
isAdd = false ; // 'U' bit is set as part of the fixup.
@@ -821,7 +821,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
+ Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
Imm8 = 0;
isAdd = false ; // 'U' bit is set as part of the fixup.
@@ -857,7 +857,7 @@ getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
// {7-0} = imm8
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
- unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
unsigned Imm8 = MO1.getImm();
return (Reg << 8) | Imm8;
}
@@ -940,8 +940,8 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
const MCOperand &MO2 = MI.getOperand(OpIdx+2);
- unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
- unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
+ unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
@@ -975,7 +975,7 @@ getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
// {12} isAdd
// {11-0} imm12/Rm
const MCOperand &MO = MI.getOperand(OpIdx);
- unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
Binary |= Rn << 14;
return Binary;
@@ -998,7 +998,7 @@ getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
Binary <<= 7; // Shift amount is bits [11:7]
Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
- Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
+ Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
}
return Binary | (isAdd << 12) | (isReg << 13);
}
@@ -1011,7 +1011,7 @@ getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
bool isAdd = MO1.getImm() != 0;
- return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
+ return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
}
uint32_t ARMMCCodeEmitter::
@@ -1029,7 +1029,7 @@ getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
if (!isImm)
- Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
return Imm8 | (isAdd << 8) | (isImm << 9);
}
@@ -1047,7 +1047,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
// If The first operand isn't a register, we have a label reference.
if (!MO.isReg()) {
- unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
@@ -1057,14 +1057,14 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
++MCNumCPRelocations;
return (Rn << 9) | (1 << 13);
}
- unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
unsigned Imm = MO2.getImm();
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
bool isImm = MO1.getReg() == 0;
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
if (!isImm)
- Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
+ Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
}
@@ -1092,7 +1092,7 @@ getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
// {2-0} = Rn
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
- unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
unsigned Imm5 = MO1.getImm();
return ((Imm5 & 0x1f) << 3) | Rn;
}
@@ -1119,7 +1119,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
+ Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
Imm8 = 0;
isAdd = false; // 'U' bit is handled as part of the fixup.
@@ -1165,7 +1165,7 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
// Encode Rm.
- unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
// Encode the shift opcode.
unsigned SBits = 0;
@@ -1190,7 +1190,7 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
// Encode the shift operation Rs.
// Encode Rs bit[11:8].
assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
- return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
+ return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
}
unsigned ARMMCCodeEmitter::
@@ -1209,7 +1209,7 @@ getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
// Encode Rm.
- unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
// Encode the shift opcode.
unsigned SBits = 0;
@@ -1248,9 +1248,9 @@ getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
// Encoded as [Rn, Rm, imm].
// FIXME: Needs fixup support.
- unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
+ unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
Value <<= 4;
- Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
+ Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
Value <<= 2;
Value |= MO3.getImm();
@@ -1264,7 +1264,7 @@ getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
const MCOperand &MO2 = MI.getOperand(OpNum+1);
// FIXME: Needs fixup support.
- unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
+ unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
// Even though the immediate is 8 bits long, we need 9 bits in order
// to represent the (inverse of the) sign bit.
@@ -1326,7 +1326,7 @@ getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
// Encode Rm.
- unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
// Encode the shift opcode.
unsigned SBits = 0;
@@ -1382,7 +1382,7 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op,
if (SPRRegs || DPRRegs) {
// VLDM/VSTM
- unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
+ unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
Binary |= (RegNo & 0x1f) << 8;
if (SPRRegs)
@@ -1391,7 +1391,7 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op,
Binary |= NumRegs * 2;
} else {
for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
- unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
+ unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
Binary |= 1 << RegNo;
}
}
@@ -1407,7 +1407,7 @@ getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op + 1);
- unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
+ unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
unsigned Align = 0;
switch (Imm.getImm()) {
@@ -1430,7 +1430,7 @@ getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op + 1);
- unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
+ unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
unsigned Align = 0;
switch (Imm.getImm()) {
@@ -1456,7 +1456,7 @@ getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op + 1);
- unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
+ unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
unsigned Align = 0;
switch (Imm.getImm()) {
@@ -1475,7 +1475,7 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(Op);
if (MO.getReg() == 0) return 0x0D;
- return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
}
unsigned ARMMCCodeEmitter::
diff --git a/lib/Target/Mangler.cpp b/lib/Target/Mangler.cpp
index 2269b739d8..dc70259880 100644
--- a/lib/Target/Mangler.cpp
+++ b/lib/Target/Mangler.cpp
@@ -47,18 +47,18 @@ static void MangleLetter(SmallVectorImpl<char> &OutName, unsigned char C) {
/// NameNeedsEscaping - Return true if the identifier \p Str needs quotes
/// for this assembler.
-static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo &MAI) {
+static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo *MAI) {
assert(!Str.empty() && "Cannot create an empty MCSymbol");
// If the first character is a number and the target does not allow this, we
// need quotes.
- if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
+ if (!MAI->doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
return true;
// If any of the characters in the string is an unacceptable character, force
// quotes.
- bool AllowPeriod = MAI.doesAllowPeriodsInName();
- bool AllowUTF8 = MAI.doesAllowUTF8();
+ bool AllowPeriod = MAI->doesAllowPeriodsInName();
+ bool AllowUTF8 = MAI->doesAllowUTF8();
for (unsigned i = 0, e = Str.size(); i != e; ++i)
if (!isAcceptableChar(Str[i], AllowPeriod, AllowUTF8))
return true;
@@ -68,16 +68,16 @@ static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo &MAI) {
/// appendMangledName - Add the specified string in mangled form if it uses
/// any unusual characters.
static void appendMangledName(SmallVectorImpl<char> &OutName, StringRef Str,
- const MCAsmInfo &MAI) {
+ const MCAsmInfo *MAI) {
// The first character is not allowed to be a number unless the target
// explicitly allows it.
- if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
+ if (!MAI->doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
MangleLetter(OutName, Str[0]);
Str = Str.substr(1);
}
- bool AllowPeriod = MAI.doesAllowPeriodsInName();
- bool AllowUTF8 = MAI.doesAllowUTF8();
+ bool AllowPeriod = MAI->doesAllowPeriodsInName();
+ bool AllowUTF8 = MAI->doesAllowUTF8();
for (unsigned i = 0, e = Str.size(); i != e; ++i) {
if (!isAcceptableChar(Str[i], AllowPeriod, AllowUTF8))
MangleLetter(OutName, Str[i]);
@@ -110,21 +110,21 @@ void Mangler::getNameWithPrefix(SmallVectorImpl<char> &OutName,
StringRef Name = GVName.toStringRef(TmpData);
assert(!Name.empty() && "getNameWithPrefix requires non-empty name");
- const MCAsmInfo &MAI = Context.getAsmInfo();
+ const MCAsmInfo *MAI = Context.getAsmInfo();
// If the global name is not led with \1, add the appropriate prefixes.
if (Name[0] == '\1') {
Name = Name.substr(1);
} else {
if (PrefixTy == Mangler::Private) {
- const char *Prefix = MAI.getPrivateGlobalPrefix();
+ const char *Prefix = MAI->getPrivateGlobalPrefix();
OutName.append(Prefix, Prefix+strlen(Prefix));
} else if (PrefixTy == Mangler::LinkerPrivate) {
- const char *Prefix = MAI.getLinkerPrivateGlobalPrefix();
+ const char *Prefix = MAI->getLinkerPrivateGlobalPrefix();
OutName.append(Prefix, Prefix+strlen(Prefix));
}
- const char *Prefix = MAI.getGlobalPrefix();
+ const char *Prefix = MAI->getGlobalPrefix();
if (Prefix[0] == 0)
; // Common noop, no prefix.
else if (Prefix[1] == 0)
@@ -137,7 +137,7 @@ void Mangler::getNameWithPrefix(SmallVectorImpl<char> &OutName,
if (!NameNeedsEscaping(Name, MAI) ||
// If quotes are supported, they can be used unless the string contains
// a quote or newline.
- (MAI.doesAllowQuotesInName() &&
+ (MAI->doesAllowQuotesInName() &&
Name.find_first_of("\n\"") == StringRef::npos)) {
OutName.append(Name.begin(), Name.end());
return;
@@ -145,7 +145,7 @@ void Mangler::getNameWithPrefix(SmallVectorImpl<char> &OutName,
// On systems that do not allow quoted names, we need to mangle most
// strange characters.
- if (!MAI.doesAllowQuotesInName())
+ if (!MAI->doesAllowQuotesInName())
return appendMangledName(OutName, Name, MAI);
// Okay, the system allows quoted strings. We can quote most anything, the
@@ -207,7 +207,7 @@ void Mangler::getNameWithPrefix(SmallVectorImpl<char> &OutName,
// If we are supposed to add a microsoft-style suffix for stdcall/fastcall,
// add it.
- if (Context.getAsmInfo().hasMicrosoftFastStdCallMangling()) {
+ if (Context.getAsmInfo()->hasMicrosoftFastStdCallMangling()) {
if (const Function *F = dyn_cast<Function>(GV)) {
CallingConv::ID CC = F->getCallingConv();
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index d1d69d886a..ab23d9fba6 100644
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -880,7 +880,7 @@ int MipsAsmParser::getATReg() {
}
unsigned MipsAsmParser::getReg(int RC, int RegNo) {
- return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
+ return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
}
int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index a464dfe5ac..4dc6917f4d 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -380,7 +380,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg()) {
unsigned Reg = MO.getReg();
- unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
+ unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
return RegNo;
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
diff --git a/lib/Target/Mips/Mips16FrameLowering.cpp b/lib/Target/Mips/Mips16FrameLowering.cpp
index e180c49236..9fde614f30 100644
--- a/lib/Target/Mips/Mips16FrameLowering.cpp
+++ b/lib/Target/Mips/Mips16FrameLowering.cpp
@@ -40,7 +40,7 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const {
if (StackSize == 0 && !MFI->adjustsStack()) return;
MachineModuleInfo &MMI = MF.getMMI();
- const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
MachineLocation DstML, SrcML;
// Adjust stack.
@@ -56,13 +56,13 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const {
MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl,
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
- unsigned S1 = MRI.getDwarfRegNum(Mips::S1, true);
+ unsigned S1 = MRI->getDwarfRegNum(Mips::S1, true);
MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S1, -8));
- unsigned S0 = MRI.getDwarfRegNum(Mips::S0, true);
+ unsigned S0 = MRI->getDwarfRegNum(Mips::S0, true);
MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S0, -12));
- unsigned RA = MRI.getDwarfRegNum(Mips::RA, true);
+ unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4));
if (hasFP(MF))
diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp
index 91ffb94a06..c8d83882e0 100644
--- a/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -285,7 +285,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
if (StackSize == 0 && !MFI->adjustsStack()) return;
MachineModuleInfo &MMI = MF.getMMI();
- const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
MachineLocation DstML, SrcML;
// Adjust stack.
@@ -321,9 +321,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
// one for each of the paired single precision registers.
if (Mips::AFGR64RegClass.contains(Reg)) {
unsigned Reg0 =
- MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
+ MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
unsigned Reg1 =
- MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
+ MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
if (!STI.isLittle())
std::swap(Reg0, Reg1);
@@ -335,7 +335,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
} else {
// Reg is either in CPURegs or FGR32.
MMI.addFrameInst(MCCFIInstruction::createOffset(
- CSLabel, MRI.getDwarfRegNum(Reg, 1), Offset));
+ CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
}
}
}
@@ -358,7 +358,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
for (int I = 0; I < 4; ++I) {
int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
- unsigned Reg = MRI.getDwarfRegNum(ehDataReg(I), true);
+ unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
}
}
@@ -373,7 +373,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
BuildMI(MBB, MBBI, dl,
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
- SetFPLabel, MRI.getDwarfRegNum(FP, true)));
+ SetFPLabel, MRI->getDwarfRegNum(FP, true)));
}
}
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 31c73aeff5..420c01ba9e 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -191,7 +191,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
// Return the thread-pointer register's encoding.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_tlsreg));
- return CTX.getRegisterInfo().getEncodingValue(PPC::X13);
+ return CTX.getRegisterInfo()->getEncodingValue(PPC::X13);
}
unsigned PPCMCCodeEmitter::
@@ -202,7 +202,7 @@ get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
MI.getOpcode() == PPC::MFOCRF ||
MI.getOpcode() == PPC::MTCRF8) &&
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
- return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
}
@@ -214,7 +214,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
// The GPR operand should come through here though.
assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
- return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
+ return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
}
assert(MO.isImm() &&
diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp
index dabe61348d..dc734d1348 100644
--- a/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -334,7 +334,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
*static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
MachineModuleInfo &MMI = MF.getMMI();
- const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
DebugLoc dl;
bool needsFrameMoves = MMI.hasDebugInfo() ||
MF.getFunction()->needsUnwindTableEntry();
@@ -530,14 +530,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
if (HasFP) {
unsigned Reg = isPPC64 ? PPC::X31 : PPC::R31;
- Reg = MRI.getDwarfRegNum(Reg, true);
+ Reg = MRI->getDwarfRegNum(Reg, true);
MMI.addFrameInst(
MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
}
if (MustSaveLR) {
unsigned Reg = isPPC64 ? PPC::LR8 : PPC::LR;
- Reg = MRI.getDwarfRegNum(Reg, true);
+ Reg = MRI->getDwarfRegNum(Reg, true);
MMI.addFrameInst(
MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset));
}
@@ -565,7 +565,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
unsigned Reg = HasFP ? (isPPC64 ? PPC::X31 : PPC::R31)
: (isPPC64 ? PPC::X1 : PPC::R1);
- Reg = MRI.getDwarfRegNum(Reg, true);
+ Reg = MRI->getDwarfRegNum(Reg, true);
MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
}
}
@@ -597,13 +597,13 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
&& Subtarget.isPPC64()
&& (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
MMI.addFrameInst(MCCFIInstruction::createOffset(
- Label, MRI.getDwarfRegNum(PPC::CR2, true), 8));
+ Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
continue;
}
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
MMI.addFrameInst(MCCFIInstruction::createOffset(
- Label, MRI.getDwarfRegNum(Reg, true), Offset));
+ Label, MRI->getDwarfRegNum(Reg, true), Offset));
}
}
}
diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
index 7721b1ffab..f8f8998a54 100644
--- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
+++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
@@ -112,7 +112,7 @@ uint64_t SystemZMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
if (MO.isReg())
- return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
+ return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
if (MO.isImm())
return static_cast<uint64_t>(MO.getImm());
llvm_unreachable("Unexpected operand type!");
diff --git a/lib/Target/SystemZ/SystemZFrameLowering.cpp b/lib/Target/SystemZ/SystemZFrameLowering.cpp
index c0d72c3b7d..43f1e47918 100644
--- a/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -297,7 +297,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineModuleInfo &MMI = MF.getMMI();
- const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
bool HasFP = hasFP(MF);
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
@@ -322,7 +322,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
if (SystemZ::GR64BitRegClass.contains(Reg)) {
int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
MMI.addFrameInst(MCCFIInstruction::createOffset(
- GPRSaveLabel, MRI.getDwarfRegNum(Reg, true), Offset));
+ GPRSaveLabel, MRI->getDwarfRegNum(Reg, true), Offset));
}
}
}
@@ -351,7 +351,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::PROLOG_LABEL))
.addSym(SetFPLabel);
- unsigned HardFP = MRI.getDwarfRegNum(SystemZ::R11D, true);
+ unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
MMI.addFrameInst(
MCCFIInstruction::createDefCfaRegister(SetFPLabel, HardFP));
@@ -379,7 +379,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
// Add CFI for the this save.
if (!FPRSaveLabel)
FPRSaveLabel = MMI.getContext().CreateTempSymbol();
- unsigned Reg = MRI.getDwarfRegNum(I->getReg(), true);
+ unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
int64_t Offset = getFrameIndexOffset(MF, I->getFrameIdx());
MMI.addFrameInst(MCCFIInstruction::createOffset(
FPRSaveLabel, Reg, SPOffsetFromCFA + Offset));
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 016af71501..3e450fd9af 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -53,7 +53,7 @@ public:
}
unsigned GetX86RegNum(const MCOperand &MO) const {
- return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7;
+ return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
}
// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp
index 3061117c4d..9d66bfd88a 100644
--- a/lib/Target/X86/X86FrameLowering.cpp
+++ b/lib/Target/X86/X86FrameLowering.cpp
@@ -307,7 +307,7 @@ void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
unsigned FramePtr) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo &MMI = MF.getMMI();
- const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
+ const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
// Add callee saved registers to move list.
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
@@ -360,7 +360,7 @@ void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
if (HasFP && FramePtr == Reg)
continue;
- unsigned DwarfReg = MRI.getDwarfRegNum(Reg, true);
+ unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
MMI.addFrameInst(MCCFIInstruction::createOffset(Label, DwarfReg, Offset));
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 09:51:06 +0000