diff options
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/R600/AMDGPU.h | 6 | ||||
-rw-r--r-- | lib/Target/R600/AMDILISelDAGToDAG.cpp | 21 | ||||
-rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 42 | ||||
-rw-r--r-- | lib/Target/R600/R600Instructions.td | 2 |
4 files changed, 22 insertions, 49 deletions
diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h index 7621422a1f..fbf1fcee58 100644 --- a/lib/Target/R600/AMDGPU.h +++ b/lib/Target/R600/AMDGPU.h @@ -74,6 +74,12 @@ enum AddressSpaces { ADDRESS_NONE = 5, ///< Address space for unknown memory. PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) + + // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this + // order to be able to dynamically index a constant buffer, for example: + // + // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx + CONSTANT_BUFFER_0 = 8, CONSTANT_BUFFER_1 = 9, CONSTANT_BUFFER_2 = 10, diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp index e79ab3c0db..78036a8a14 100644 --- a/lib/Target/R600/AMDILISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp @@ -565,24 +565,11 @@ bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) { return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS); } -bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) const { - if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) { - return true; - } - - const DataLayout *DL = TM.getDataLayout(); - MachineMemOperand *MMO = N->getMemOperand(); - const Value *V = MMO->getValue(); - const Value *BV = GetUnderlyingObject(V, DL, 0); - if (MMO - && MMO->getValue() - && ((V && dyn_cast<GlobalValue>(V)) - || (BV && dyn_cast<GlobalValue>( - GetUnderlyingObject(MMO->getValue(), DL, 0))))) { - return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS); - } else { - return false; +bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const { + if (CbId == -1) { + return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS); } + return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_BUFFER_0 + CbId); } bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const { diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 7f93f23f28..dd613d56a6 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -72,10 +72,10 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setOperationAction(ISD::LOAD, MVT::i32, Custom); setOperationAction(ISD::LOAD, MVT::v2i32, Expand); setOperationAction(ISD::LOAD, MVT::v4i32, Custom); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); + setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom); + setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom); setOperationAction(ISD::STORE, MVT::i8, Custom); setOperationAction(ISD::STORE, MVT::i32, Custom); setOperationAction(ISD::STORE, MVT::v2i32, Expand); @@ -775,7 +775,7 @@ SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, unsigned DwordOffset) const { unsigned ByteOffset = DwordOffset * 4; PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), - AMDGPUAS::PARAM_I_ADDRESS); + AMDGPUAS::CONSTANT_BUFFER_0); // We shouldn't be using an offset wider than 16-bits for implicit parameters. assert(isInt<16>(ByteOffset)); @@ -1219,40 +1219,20 @@ SDValue R600TargetLowering::LowerFormalArguments( AnalyzeFormalArguments(CCInfo, Ins); - Function::const_arg_iterator FuncArg = - DAG.getMachineFunction().getFunction()->arg_begin(); - for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) { + for (unsigned i = 0, e = Ins.size(); i < e; ++i) { CCValAssign &VA = ArgLocs[i]; EVT VT = VA.getLocVT(); - Type *ArgType = FuncArg->getType(); - unsigned ArgSizeInBits = ArgType->isPointerTy() ? - 32 : ArgType->getPrimitiveSizeInBits(); - unsigned ArgBytes = ArgSizeInBits >> 3; - EVT ArgVT; - if (ArgSizeInBits < VT.getSizeInBits()) { - assert(!ArgType->isFloatTy() && - "Extending floating point arguments not supported yet"); - ArgVT = MVT::getIntegerVT(ArgSizeInBits); - } else { - ArgVT = VT; - } - - ISD::LoadExtType LoadType = ISD::EXTLOAD; - if (Ins[i].Flags.isZExt()) { - LoadType = ISD::ZEXTLOAD; - } else if (Ins[i].Flags.isSExt()) { - LoadType = ISD::SEXTLOAD; - } PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), - AMDGPUAS::PARAM_I_ADDRESS); + AMDGPUAS::CONSTANT_BUFFER_0); // The first 36 bytes of the input buffer contains information about // thread group and global sizes. - SDValue Arg = DAG.getExtLoad(LoadType, DL, VT, DAG.getRoot(), + SDValue Arg = DAG.getLoad(VT, DL, Chain, DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32), - MachinePointerInfo(UndefValue::get(PtrTy)), - ArgVT, false, false, ArgBytes); + MachinePointerInfo(UndefValue::get(PtrTy)), false, + false, false, 4); // 4 is the prefered alignment for + // the CONSTANT memory space. InVals.push_back(Arg); } return Chain; diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index 8a49a8df1d..632cbcf48a 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -313,7 +313,7 @@ class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern> class LoadParamFrag <PatFrag load_type> : PatFrag < (ops node:$ptr), (load_type node:$ptr), - [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }] + [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }] >; def load_param : LoadParamFrag<load>; |