summaryrefslogtreecommitdiff
path: root/lib
diff options
context:
space:
mode:
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/CMakeLists.txt1
-rw-r--r--lib/CodeGen/InlineSpiller.cpp136
-rw-r--r--lib/CodeGen/Spiller.cpp11
3 files changed, 147 insertions, 1 deletions
diff --git a/lib/CodeGen/CMakeLists.txt b/lib/CodeGen/CMakeLists.txt
index d7f673727c..0501350de6 100644
--- a/lib/CodeGen/CMakeLists.txt
+++ b/lib/CodeGen/CMakeLists.txt
@@ -13,6 +13,7 @@ add_llvm_library(LLVMCodeGen
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp
+ InlineSpiller.cpp
IntrinsicLowering.cpp
LLVMTargetMachine.cpp
LatencyPriorityQueue.cpp
diff --git a/lib/CodeGen/InlineSpiller.cpp b/lib/CodeGen/InlineSpiller.cpp
new file mode 100644
index 0000000000..a7a774d1ca
--- /dev/null
+++ b/lib/CodeGen/InlineSpiller.cpp
@@ -0,0 +1,136 @@
+//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// The inline spiller modifies the machine function directly instead of
+// inserting spills and restores in VirtRegMap.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "spiller"
+#include "Spiller.h"
+#include "VirtRegMap.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace {
+class InlineSpiller : public Spiller {
+ MachineFunction &mf_;
+ LiveIntervals &lis_;
+ VirtRegMap &vrm_;
+ MachineFrameInfo &mfi_;
+ MachineRegisterInfo &mri_;
+ const TargetInstrInfo &tii_;
+ const TargetRegisterInfo &tri_;
+
+ ~InlineSpiller() {}
+
+public:
+ InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
+ : mf_(*mf), lis_(*lis), vrm_(*vrm),
+ mfi_(*mf->getFrameInfo()),
+ mri_(mf->getRegInfo()),
+ tii_(*mf->getTarget().getInstrInfo()),
+ tri_(*mf->getTarget().getRegisterInfo()) {}
+
+ void spill(LiveInterval *li,
+ std::vector<LiveInterval*> &newIntervals,
+ SmallVectorImpl<LiveInterval*> &spillIs,
+ SlotIndex *earliestIndex);
+};
+}
+
+namespace llvm {
+Spiller *createInlineSpiller(MachineFunction *mf,
+ LiveIntervals *lis,
+ const MachineLoopInfo *mli,
+ VirtRegMap *vrm) {
+ return new InlineSpiller(mf, lis, vrm);
+}
+}
+
+void InlineSpiller::spill(LiveInterval *li,
+ std::vector<LiveInterval*> &newIntervals,
+ SmallVectorImpl<LiveInterval*> &spillIs,
+ SlotIndex *earliestIndex) {
+ DEBUG(dbgs() << "Inline spilling " << *li << "\n");
+ assert(li->isSpillable() && "Attempting to spill already spilled value.");
+ assert(!li->isStackSlot() && "Trying to spill a stack slot.");
+
+ const TargetRegisterClass *RC = mri_.getRegClass(li->reg);
+ unsigned SS = vrm_.assignVirt2StackSlot(li->reg);
+
+ for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
+ MachineInstr *MI = RI.skipInstruction();) {
+ SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
+
+ // Analyze instruction.
+ bool Reads, Writes;
+ SmallVector<unsigned, 8> Ops;
+ tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
+
+ // Allocate interval around instruction.
+ // FIXME: Infer regclass from instruction alone.
+ unsigned NewVReg = mri_.createVirtualRegister(RC);
+ vrm_.grow();
+ LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
+ NewLI.markNotSpillable();
+
+ // Reload if instruction reads register.
+ if (Reads) {
+ MachineBasicBlock::iterator MII = MI;
+ tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_);
+ --MII; // Point to load instruction.
+ SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
+ DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MII);
+ VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
+ lis_.getVNInfoAllocator());
+ NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
+ }
+
+ // Rewrite instruction operands.
+ bool hasLiveDef = false;
+ for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(Ops[i]);
+ MO.setReg(NewVReg);
+ if (MO.isUse()) {
+ if (!MI->isRegTiedToDefOperand(Ops[i]))
+ MO.setIsKill();
+ } else {
+ if (!MO.isDead())
+ hasLiveDef = true;
+ }
+ }
+ DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
+
+ // Spill is instruction writes register.
+ // FIXME: Use a second vreg if instruction has no tied ops.
+ if (Writes && hasLiveDef) {
+ MachineBasicBlock::iterator MII = MI;
+ tii_.storeRegToStackSlot(*MI->getParent(), ++MII, NewVReg, true, SS, RC,
+ &tri_);
+ --MII; // Point to store instruction.
+ SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
+ DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII);
+ VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
+ lis_.getVNInfoAllocator());
+ NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
+ }
+
+ DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
+ newIntervals.push_back(&NewLI);
+ }
+}
diff --git a/lib/CodeGen/Spiller.cpp b/lib/CodeGen/Spiller.cpp
index aed18ed9ac..f4d6024f97 100644
--- a/lib/CodeGen/Spiller.cpp
+++ b/lib/CodeGen/Spiller.cpp
@@ -26,7 +26,7 @@
using namespace llvm;
namespace {
- enum SpillerName { trivial, standard, splitting };
+ enum SpillerName { trivial, standard, splitting, inline_ };
}
static cl::opt<SpillerName>
@@ -36,6 +36,7 @@ spillerOpt("spiller",
cl::values(clEnumVal(trivial, "trivial spiller"),
clEnumVal(standard, "default spiller"),
clEnumVal(splitting, "splitting spiller"),
+ "inline", inline_, "inline spiller",
clEnumValEnd),
cl::init(standard));
@@ -506,6 +507,13 @@ private:
} // end anonymous namespace
+namespace llvm {
+Spiller *createInlineSpiller(MachineFunction*,
+ LiveIntervals*,
+ const MachineLoopInfo*,
+ VirtRegMap*);
+}
+
llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
const MachineLoopInfo *loopInfo,
VirtRegMap *vrm) {
@@ -514,5 +522,6 @@ llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
case trivial: return new TrivialSpiller(mf, lis, vrm);
case standard: return new StandardSpiller(lis, loopInfo, vrm);
case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm);
+ case inline_: return createInlineSpiller(mf, lis, loopInfo, vrm);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 23:04:23 +0000