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-rw-r--r--test/CodeGen/AArch64/zero-reg.ll8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/AArch64/zero-reg.ll b/test/CodeGen/AArch64/zero-reg.ll
index 9b1e52770c..c4073cba08 100644
--- a/test/CodeGen/AArch64/zero-reg.ll
+++ b/test/CodeGen/AArch64/zero-reg.ll
@@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-linux-gnu | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0
@@ -7,9 +8,9 @@ define void @test_zr() {
; CHECK-LABEL: test_zr:
store i32 0, i32* @var32
-; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
+; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32]
store i64 0, i64* @var64
-; CHECK: str xzr, [{{x[0-9]+}}, #:lo12:var64]
+; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64]
ret void
; CHECK: ret
@@ -23,8 +24,7 @@ define void @test_sp(i32 %val) {
; instruction (0b11111 in the Rn field would mean "sp").
%addr = getelementptr i32* null, i64 0
store i32 %val, i32* %addr
-; CHECK: mov x[[NULL:[0-9]+]], xzr
-; CHECK: str {{w[0-9]+}}, [x[[NULL]]]
+; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}]
ret void
; CHECK: ret