diff options
Diffstat (limited to 'test/CodeGen/AArch64')
| -rw-r--r-- | test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-simd-ldst-multi-elem.ll | 420 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-simd-ldst-one.ll | 294 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-simd-ldst.ll | 24 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll | 56 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-simd-post-ldst-one.ll | 36 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-simd-tbl.ll | 144 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/neon-truncStore-extLoad.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll | 86 |
9 files changed, 536 insertions, 536 deletions
diff --git a/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll b/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll index 9f2f876d34..186a76909e 100644 --- a/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll +++ b/test/CodeGen/AArch64/neon-copyPhysReg-tuple.ll @@ -5,7 +5,7 @@ define <4 x i32> @copyTuple.QPair(i8* %a, i8* %b) { ; CHECK-LABEL: copyTuple.QPair: ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x{{[0-9]+|sp}}] +; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}] entry: %vld = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i32 0, i32 4) %extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0 @@ -19,7 +19,7 @@ define <4 x i32> @copyTuple.QTriple(i8* %a, i8* %b, <4 x i32> %c) { ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x{{[0-9]+|sp}}] +; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}] entry: %vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i32 0, i32 4) %extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0 @@ -34,7 +34,7 @@ define <4 x i32> @copyTuple.QQuad(i8* %a, i8* %b, <4 x i32> %c) { ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b ; CHECK: orr v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b -; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x{{[0-9]+|sp}}] +; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x{{[0-9]+|sp}}] entry: %vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8* %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, <4 x i32> %c, i32 0, i32 4) %extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld, 0 diff --git a/test/CodeGen/AArch64/neon-simd-ldst-multi-elem.ll b/test/CodeGen/AArch64/neon-simd-ldst-multi-elem.ll index 34056c7d56..a3b160413f 100644 --- a/test/CodeGen/AArch64/neon-simd-ldst-multi-elem.ll +++ b/test/CodeGen/AArch64/neon-simd-ldst-multi-elem.ll @@ -5,8 +5,8 @@ define void @test_ldst1_v16i8(<16 x i8>* %ptr, <16 x i8>* %ptr2) { ; CHECK-LABEL: test_ldst1_v16i8: -; CHECK: ld1 {v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}] %tmp = load <16 x i8>* %ptr store <16 x i8> %tmp, <16 x i8>* %ptr2 ret void @@ -14,8 +14,8 @@ define void @test_ldst1_v16i8(<16 x i8>* %ptr, <16 x i8>* %ptr2) { define void @test_ldst1_v8i16(<8 x i16>* %ptr, <8 x i16>* %ptr2) { ; CHECK-LABEL: test_ldst1_v8i16: -; CHECK: ld1 {v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}] %tmp = load <8 x i16>* %ptr store <8 x i16> %tmp, <8 x i16>* %ptr2 ret void @@ -23,8 +23,8 @@ define void @test_ldst1_v8i16(<8 x i16>* %ptr, <8 x i16>* %ptr2) { define void @test_ldst1_v4i32(<4 x i32>* %ptr, <4 x i32>* %ptr2) { ; CHECK-LABEL: test_ldst1_v4i32: -; CHECK: ld1 {v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %tmp = load <4 x i32>* %ptr store <4 x i32> %tmp, <4 x i32>* %ptr2 ret void @@ -32,8 +32,8 @@ define void @test_ldst1_v4i32(<4 x i32>* %ptr, <4 x i32>* %ptr2) { define void @test_ldst1_v2i64(<2 x i64>* %ptr, <2 x i64>* %ptr2) { ; CHECK-LABEL: test_ldst1_v2i64: -; CHECK: ld1 {v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %tmp = load <2 x i64>* %ptr store <2 x i64> %tmp, <2 x i64>* %ptr2 ret void @@ -41,8 +41,8 @@ define void @test_ldst1_v2i64(<2 x i64>* %ptr, <2 x i64>* %ptr2) { define void @test_ldst1_v8i8(<8 x i8>* %ptr, <8 x i8>* %ptr2) { ; CHECK-LABEL: test_ldst1_v8i8: -; CHECK: ld1 {v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] %tmp = load <8 x i8>* %ptr store <8 x i8> %tmp, <8 x i8>* %ptr2 ret void @@ -50,8 +50,8 @@ define void @test_ldst1_v8i8(<8 x i8>* %ptr, <8 x i8>* %ptr2) { define void @test_ldst1_v4i16(<4 x i16>* %ptr, <4 x i16>* %ptr2) { ; CHECK-LABEL: test_ldst1_v4i16: -; CHECK: ld1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] %tmp = load <4 x i16>* %ptr store <4 x i16> %tmp, <4 x i16>* %ptr2 ret void @@ -59,8 +59,8 @@ define void @test_ldst1_v4i16(<4 x i16>* %ptr, <4 x i16>* %ptr2) { define void @test_ldst1_v2i32(<2 x i32>* %ptr, <2 x i32>* %ptr2) { ; CHECK-LABEL: test_ldst1_v2i32: -; CHECK: ld1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %tmp = load <2 x i32>* %ptr store <2 x i32> %tmp, <2 x i32>* %ptr2 ret void @@ -68,8 +68,8 @@ define void @test_ldst1_v2i32(<2 x i32>* %ptr, <2 x i32>* %ptr2) { define void @test_ldst1_v1i64(<1 x i64>* %ptr, <1 x i64>* %ptr2) { ; CHECK-LABEL: test_ldst1_v1i64: -; CHECK: ld1 {v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] -; CHECK: st1 {v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %tmp = load <1 x i64>* %ptr store <1 x i64> %tmp, <1 x i64>* %ptr2 ret void @@ -115,14 +115,14 @@ define void @test_ldst1_v1i64(<1 x i64>* %ptr, <1 x i64>* %ptr2) { define <16 x i8> @test_vld1q_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld1q_s8 -; CHECK: ld1 {v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}] %vld1 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %a, i32 1) ret <16 x i8> %vld1 } define <8 x i16> @test_vld1q_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld1q_s16 -; CHECK: ld1 {v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld1 = tail call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %1, i32 2) ret <8 x i16> %vld1 @@ -130,7 +130,7 @@ define <8 x i16> @test_vld1q_s16(i16* readonly %a) { define <4 x i32> @test_vld1q_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld1q_s32 -; CHECK: ld1 {v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld1 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %1, i32 4) ret <4 x i32> %vld1 @@ -138,7 +138,7 @@ define <4 x i32> @test_vld1q_s32(i32* readonly %a) { define <2 x i64> @test_vld1q_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld1q_s64 -; CHECK: ld1 {v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld1 = tail call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %1, i32 8) ret <2 x i64> %vld1 @@ -146,7 +146,7 @@ define <2 x i64> @test_vld1q_s64(i64* readonly %a) { define <4 x float> @test_vld1q_f32(float* readonly %a) { ; CHECK-LABEL: test_vld1q_f32 -; CHECK: ld1 {v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %1, i32 4) ret <4 x float> %vld1 @@ -154,7 +154,7 @@ define <4 x float> @test_vld1q_f32(float* readonly %a) { define <2 x double> @test_vld1q_f64(double* readonly %a) { ; CHECK-LABEL: test_vld1q_f64 -; CHECK: ld1 {v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld1 = tail call <2 x double> @llvm.arm.neon.vld1.v2f64(i8* %1, i32 8) ret <2 x double> %vld1 @@ -162,14 +162,14 @@ define <2 x double> @test_vld1q_f64(double* readonly %a) { define <8 x i8> @test_vld1_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld1_s8 -; CHECK: ld1 {v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %a, i32 1) ret <8 x i8> %vld1 } define <4 x i16> @test_vld1_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld1_s16 -; CHECK: ld1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld1 = tail call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %1, i32 2) ret <4 x i16> %vld1 @@ -177,7 +177,7 @@ define <4 x i16> @test_vld1_s16(i16* readonly %a) { define <2 x i32> @test_vld1_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld1_s32 -; CHECK: ld1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld1 = tail call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %1, i32 4) ret <2 x i32> %vld1 @@ -185,7 +185,7 @@ define <2 x i32> @test_vld1_s32(i32* readonly %a) { define <1 x i64> @test_vld1_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld1_s64 -; CHECK: ld1 {v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld1 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %1, i32 8) ret <1 x i64> %vld1 @@ -193,7 +193,7 @@ define <1 x i64> @test_vld1_s64(i64* readonly %a) { define <2 x float> @test_vld1_f32(float* readonly %a) { ; CHECK-LABEL: test_vld1_f32 -; CHECK: ld1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %1, i32 4) ret <2 x float> %vld1 @@ -201,7 +201,7 @@ define <2 x float> @test_vld1_f32(float* readonly %a) { define <1 x double> @test_vld1_f64(double* readonly %a) { ; CHECK-LABEL: test_vld1_f64 -; CHECK: ld1 {v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld1 = tail call <1 x double> @llvm.arm.neon.vld1.v1f64(i8* %1, i32 8) ret <1 x double> %vld1 @@ -209,14 +209,14 @@ define <1 x double> @test_vld1_f64(double* readonly %a) { define <8 x i8> @test_vld1_p8(i8* readonly %a) { ; CHECK-LABEL: test_vld1_p8 -; CHECK: ld1 {v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %a, i32 1) ret <8 x i8> %vld1 } define <4 x i16> @test_vld1_p16(i16* readonly %a) { ; CHECK-LABEL: test_vld1_p16 -; CHECK: ld1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld1 = tail call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %1, i32 2) ret <4 x i16> %vld1 @@ -224,7 +224,7 @@ define <4 x i16> @test_vld1_p16(i16* readonly %a) { define %struct.int8x16x2_t @test_vld2q_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld2q_s8 -; CHECK: ld2 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}] %vld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8* %a, i32 1) %vld2.fca.0.extract = extractvalue { <16 x i8>, <16 x i8> } %vld2, 0 %vld2.fca.1.extract = extractvalue { <16 x i8>, <16 x i8> } %vld2, 1 @@ -235,7 +235,7 @@ define %struct.int8x16x2_t @test_vld2q_s8(i8* readonly %a) { define %struct.int16x8x2_t @test_vld2q_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld2q_s16 -; CHECK: ld2 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld2 = tail call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2.v8i16(i8* %1, i32 2) %vld2.fca.0.extract = extractvalue { <8 x i16>, <8 x i16> } %vld2, 0 @@ -247,7 +247,7 @@ define %struct.int16x8x2_t @test_vld2q_s16(i16* readonly %a) { define %struct.int32x4x2_t @test_vld2q_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld2q_s32 -; CHECK: ld2 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32(i8* %1, i32 4) %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0 @@ -259,7 +259,7 @@ define %struct.int32x4x2_t @test_vld2q_s32(i32* readonly %a) { define %struct.int64x2x2_t @test_vld2q_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld2q_s64 -; CHECK: ld2 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld2 = tail call { <2 x i64>, <2 x i64> } @llvm.arm.neon.vld2.v2i64(i8* %1, i32 8) %vld2.fca.0.extract = extractvalue { <2 x i64>, <2 x i64> } %vld2, 0 @@ -271,7 +271,7 @@ define %struct.int64x2x2_t @test_vld2q_s64(i64* readonly %a) { define %struct.float32x4x2_t @test_vld2q_f32(float* readonly %a) { ; CHECK-LABEL: test_vld2q_f32 -; CHECK: ld2 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) %vld2.fca.0.extract = extractvalue { <4 x float>, <4 x float> } %vld2, 0 @@ -283,7 +283,7 @@ define %struct.float32x4x2_t @test_vld2q_f32(float* readonly %a) { define %struct.float64x2x2_t @test_vld2q_f64(double* readonly %a) { ; CHECK-LABEL: test_vld2q_f64 -; CHECK: ld2 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld2 = tail call { <2 x double>, <2 x double> } @llvm.arm.neon.vld2.v2f64(i8* %1, i32 8) %vld2.fca.0.extract = extractvalue { <2 x double>, <2 x double> } %vld2, 0 @@ -295,7 +295,7 @@ define %struct.float64x2x2_t @test_vld2q_f64(double* readonly %a) { define %struct.int8x8x2_t @test_vld2_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld2_s8 -; CHECK: ld2 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] %vld2 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8(i8* %a, i32 1) %vld2.fca.0.extract = extractvalue { <8 x i8>, <8 x i8> } %vld2, 0 %vld2.fca.1.extract = extractvalue { <8 x i8>, <8 x i8> } %vld2, 1 @@ -306,7 +306,7 @@ define %struct.int8x8x2_t @test_vld2_s8(i8* readonly %a) { define %struct.int16x4x2_t @test_vld2_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld2_s16 -; CHECK: ld2 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld2 = tail call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2.v4i16(i8* %1, i32 2) %vld2.fca.0.extract = extractvalue { <4 x i16>, <4 x i16> } %vld2, 0 @@ -318,7 +318,7 @@ define %struct.int16x4x2_t @test_vld2_s16(i16* readonly %a) { define %struct.int32x2x2_t @test_vld2_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld2_s32 -; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld2 = tail call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8* %1, i32 4) %vld2.fca.0.extract = extractvalue { <2 x i32>, <2 x i32> } %vld2, 0 @@ -330,7 +330,7 @@ define %struct.int32x2x2_t @test_vld2_s32(i32* readonly %a) { define %struct.int64x1x2_t @test_vld2_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld2_s64 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld2 = tail call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2.v1i64(i8* %1, i32 8) %vld2.fca.0.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2, 0 @@ -342,7 +342,7 @@ define %struct.int64x1x2_t @test_vld2_s64(i64* readonly %a) { define %struct.float32x2x2_t @test_vld2_f32(float* readonly %a) { ; CHECK-LABEL: test_vld2_f32 -; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld2 = tail call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2.v2f32(i8* %1, i32 4) %vld2.fca.0.extract = extractvalue { <2 x float>, <2 x float> } %vld2, 0 @@ -354,7 +354,7 @@ define %struct.float32x2x2_t @test_vld2_f32(float* readonly %a) { define %struct.float64x1x2_t @test_vld2_f64(double* readonly %a) { ; CHECK-LABEL: test_vld2_f64 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld2 = tail call { <1 x double>, <1 x double> } @llvm.arm.neon.vld2.v1f64(i8* %1, i32 8) %vld2.fca.0.extract = extractvalue { <1 x double>, <1 x double> } %vld2, 0 @@ -366,7 +366,7 @@ define %struct.float64x1x2_t @test_vld2_f64(double* readonly %a) { define %struct.int8x16x3_t @test_vld3q_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld3q_s8 -; CHECK: ld3 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}] %vld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %a, i32 1) %vld3.fca.0.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld3, 0 %vld3.fca.1.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld3, 1 @@ -379,7 +379,7 @@ define %struct.int8x16x3_t @test_vld3q_s8(i8* readonly %a) { define %struct.int16x8x3_t @test_vld3q_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld3q_s16 -; CHECK: ld3 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3.v8i16(i8* %1, i32 2) %vld3.fca.0.extract = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } %vld3, 0 @@ -393,7 +393,7 @@ define %struct.int16x8x3_t @test_vld3q_s16(i16* readonly %a) { define %struct.int32x4x3_t @test_vld3q_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld3q_s32 -; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32(i8* %1, i32 4) %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0 @@ -407,7 +407,7 @@ define %struct.int32x4x3_t @test_vld3q_s32(i32* readonly %a) { define %struct.int64x2x3_t @test_vld3q_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld3q_s64 -; CHECK: ld3 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld3.v2i64(i8* %1, i32 8) %vld3.fca.0.extract = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } %vld3, 0 @@ -421,7 +421,7 @@ define %struct.int64x2x3_t @test_vld3q_s64(i64* readonly %a) { define %struct.float32x4x3_t @test_vld3q_f32(float* readonly %a) { ; CHECK-LABEL: test_vld3q_f32 -; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32(i8* %1, i32 4) %vld3.fca.0.extract = extractvalue { <4 x float>, <4 x float>, <4 x float> } %vld3, 0 @@ -435,7 +435,7 @@ define %struct.float32x4x3_t @test_vld3q_f32(float* readonly %a) { define %struct.float64x2x3_t @test_vld3q_f64(double* readonly %a) { ; CHECK-LABEL: test_vld3q_f64 -; CHECK: ld3 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld3.v2f64(i8* %1, i32 8) %vld3.fca.0.extract = extractvalue { <2 x double>, <2 x double>, <2 x double> } %vld3, 0 @@ -449,7 +449,7 @@ define %struct.float64x2x3_t @test_vld3q_f64(double* readonly %a) { define %struct.int8x8x3_t @test_vld3_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld3_s8 -; CHECK: ld3 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] %vld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3.v8i8(i8* %a, i32 1) %vld3.fca.0.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld3, 0 %vld3.fca.1.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld3, 1 @@ -462,7 +462,7 @@ define %struct.int8x8x3_t @test_vld3_s8(i8* readonly %a) { define %struct.int16x4x3_t @test_vld3_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld3_s16 -; CHECK: ld3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8* %1, i32 2) %vld3.fca.0.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %vld3, 0 @@ -476,7 +476,7 @@ define %struct.int16x4x3_t @test_vld3_s16(i16* readonly %a) { define %struct.int32x2x3_t @test_vld3_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld3_s32 -; CHECK: ld3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v2i32(i8* %1, i32 4) %vld3.fca.0.extract = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %vld3, 0 @@ -490,7 +490,7 @@ define %struct.int32x2x3_t @test_vld3_s32(i32* readonly %a) { define %struct.int64x1x3_t @test_vld3_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld3_s64 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3.v1i64(i8* %1, i32 8) %vld3.fca.0.extract = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } %vld3, 0 @@ -504,7 +504,7 @@ define %struct.int64x1x3_t @test_vld3_s64(i64* readonly %a) { define %struct.float32x2x3_t @test_vld3_f32(float* readonly %a) { ; CHECK-LABEL: test_vld3_f32 -; CHECK: ld3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld3 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld3.v2f32(i8* %1, i32 4) %vld3.fca.0.extract = extractvalue { <2 x float>, <2 x float>, <2 x float> } %vld3, 0 @@ -518,7 +518,7 @@ define %struct.float32x2x3_t @test_vld3_f32(float* readonly %a) { define %struct.float64x1x3_t @test_vld3_f64(double* readonly %a) { ; CHECK-LABEL: test_vld3_f64 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neon.vld3.v1f64(i8* %1, i32 8) %vld3.fca.0.extract = extractvalue { <1 x double>, <1 x double>, <1 x double> } %vld3, 0 @@ -532,7 +532,7 @@ define %struct.float64x1x3_t @test_vld3_f64(double* readonly %a) { define %struct.int8x16x4_t @test_vld4q_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld4q_s8 -; CHECK: ld4 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}] %vld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8* %a, i32 1) %vld4.fca.0.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld4, 0 %vld4.fca.1.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld4, 1 @@ -547,7 +547,7 @@ define %struct.int8x16x4_t @test_vld4q_s8(i8* readonly %a) { define %struct.int16x8x4_t @test_vld4q_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld4q_s16 -; CHECK: ld4 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16(i8* %1, i32 2) %vld4.fca.0.extract = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %vld4, 0 @@ -563,7 +563,7 @@ define %struct.int16x8x4_t @test_vld4q_s16(i16* readonly %a) { define %struct.int32x4x4_t @test_vld4q_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld4q_s32 -; CHECK: ld4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4.v4i32(i8* %1, i32 4) %vld4.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld4, 0 @@ -579,7 +579,7 @@ define %struct.int32x4x4_t @test_vld4q_s32(i32* readonly %a) { define %struct.int64x2x4_t @test_vld4q_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld4q_s64 -; CHECK: ld4 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld4.v2i64(i8* %1, i32 8) %vld4.fca.0.extract = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %vld4, 0 @@ -595,7 +595,7 @@ define %struct.int64x2x4_t @test_vld4q_s64(i64* readonly %a) { define %struct.float32x4x4_t @test_vld4q_f32(float* readonly %a) { ; CHECK-LABEL: test_vld4q_f32 -; CHECK: ld4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4.v4f32(i8* %1, i32 4) %vld4.fca.0.extract = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %vld4, 0 @@ -611,7 +611,7 @@ define %struct.float32x4x4_t @test_vld4q_f32(float* readonly %a) { define %struct.float64x2x4_t @test_vld4q_f64(double* readonly %a) { ; CHECK-LABEL: test_vld4q_f64 -; CHECK: ld4 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld4.v2f64(i8* %1, i32 8) %vld4.fca.0.extract = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %vld4, 0 @@ -627,7 +627,7 @@ define %struct.float64x2x4_t @test_vld4q_f64(double* readonly %a) { define %struct.int8x8x4_t @test_vld4_s8(i8* readonly %a) { ; CHECK-LABEL: test_vld4_s8 -; CHECK: ld4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}] %vld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8* %a, i32 1) %vld4.fca.0.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld4, 0 %vld4.fca.1.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld4, 1 @@ -642,7 +642,7 @@ define %struct.int8x8x4_t @test_vld4_s8(i8* readonly %a) { define %struct.int16x4x4_t @test_vld4_s16(i16* readonly %a) { ; CHECK-LABEL: test_vld4_s16 -; CHECK: ld4 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %vld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16(i8* %1, i32 2) %vld4.fca.0.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %vld4, 0 @@ -658,7 +658,7 @@ define %struct.int16x4x4_t @test_vld4_s16(i16* readonly %a) { define %struct.int32x2x4_t @test_vld4_s32(i32* readonly %a) { ; CHECK-LABEL: test_vld4_s32 -; CHECK: ld4 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %vld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4.v2i32(i8* %1, i32 4) %vld4.fca.0.extract = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %vld4, 0 @@ -674,7 +674,7 @@ define %struct.int32x2x4_t @test_vld4_s32(i32* readonly %a) { define %struct.int64x1x4_t @test_vld4_s64(i64* readonly %a) { ; CHECK-LABEL: test_vld4_s64 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %vld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4.v1i64(i8* %1, i32 8) %vld4.fca.0.extract = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %vld4, 0 @@ -690,7 +690,7 @@ define %struct.int64x1x4_t @test_vld4_s64(i64* readonly %a) { define %struct.float32x2x4_t @test_vld4_f32(float* readonly %a) { ; CHECK-LABEL: test_vld4_f32 -; CHECK: ld4 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}] +; CHECK: ld4 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}] %1 = bitcast float* %a to i8* %vld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld4.v2f32(i8* %1, i32 4) %vld4.fca.0.extract = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld4, 0 @@ -706,7 +706,7 @@ define %struct.float32x2x4_t @test_vld4_f32(float* readonly %a) { define %struct.float64x1x4_t @test_vld4_f64(double* readonly %a) { ; CHECK-LABEL: test_vld4_f64 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}] %1 = bitcast double* %a to i8* %vld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neon.vld4.v1f64(i8* %1, i32 8) %vld4.fca.0.extract = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %vld4, 0 @@ -771,14 +771,14 @@ declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neo define void @test_vst1q_s8(i8* %a, <16 x i8> %b) { ; CHECK-LABEL: test_vst1q_s8 -; CHECK: st1 {v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] tail call void @llvm.arm.neon.vst1.v16i8(i8* %a, <16 x i8> %b, i32 1) ret void } define void @test_vst1q_s16(i16* %a, <8 x i16> %b) { ; CHECK-LABEL: test_vst1q_s16 -; CHECK: st1 {v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* tail call void @llvm.arm.neon.vst1.v8i16(i8* %1, <8 x i16> %b, i32 2) ret void @@ -786,7 +786,7 @@ define void @test_vst1q_s16(i16* %a, <8 x i16> %b) { define void @test_vst1q_s32(i32* %a, <4 x i32> %b) { ; CHECK-LABEL: test_vst1q_s32 -; CHECK: st1 {v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* tail call void @llvm.arm.neon.vst1.v4i32(i8* %1, <4 x i32> %b, i32 4) ret void @@ -794,7 +794,7 @@ define void @test_vst1q_s32(i32* %a, <4 x i32> %b) { define void @test_vst1q_s64(i64* %a, <2 x i64> %b) { ; CHECK-LABEL: test_vst1q_s64 -; CHECK: st1 {v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* tail call void @llvm.arm.neon.vst1.v2i64(i8* %1, <2 x i64> %b, i32 8) ret void @@ -802,7 +802,7 @@ define void @test_vst1q_s64(i64* %a, <2 x i64> %b) { define void @test_vst1q_f32(float* %a, <4 x float> %b) { ; CHECK-LABEL: test_vst1q_f32 -; CHECK: st1 {v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* tail call void @llvm.arm.neon.vst1.v4f32(i8* %1, <4 x float> %b, i32 4) ret void @@ -810,7 +810,7 @@ define void @test_vst1q_f32(float* %a, <4 x float> %b) { define void @test_vst1q_f64(double* %a, <2 x double> %b) { ; CHECK-LABEL: test_vst1q_f64 -; CHECK: st1 {v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* tail call void @llvm.arm.neon.vst1.v2f64(i8* %1, <2 x double> %b, i32 8) ret void @@ -818,14 +818,14 @@ define void @test_vst1q_f64(double* %a, <2 x double> %b) { define void @test_vst1_s8(i8* %a, <8 x i8> %b) { ; CHECK-LABEL: test_vst1_s8 -; CHECK: st1 {v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] tail call void @llvm.arm.neon.vst1.v8i8(i8* %a, <8 x i8> %b, i32 1) ret void } define void @test_vst1_s16(i16* %a, <4 x i16> %b) { ; CHECK-LABEL: test_vst1_s16 -; CHECK: st1 {v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* tail call void @llvm.arm.neon.vst1.v4i16(i8* %1, <4 x i16> %b, i32 2) ret void @@ -833,7 +833,7 @@ define void @test_vst1_s16(i16* %a, <4 x i16> %b) { define void @test_vst1_s32(i32* %a, <2 x i32> %b) { ; CHECK-LABEL: test_vst1_s32 -; CHECK: st1 {v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* tail call void @llvm.arm.neon.vst1.v2i32(i8* %1, <2 x i32> %b, i32 4) ret void @@ -841,7 +841,7 @@ define void @test_vst1_s32(i32* %a, <2 x i32> %b) { define void @test_vst1_s64(i64* %a, <1 x i64> %b) { ; CHECK-LABEL: test_vst1_s64 -; CHECK: st1 {v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* tail call void @llvm.arm.neon.vst1.v1i64(i8* %1, <1 x i64> %b, i32 8) ret void @@ -849,7 +849,7 @@ define void @test_vst1_s64(i64* %a, <1 x i64> %b) { define void @test_vst1_f32(float* %a, <2 x float> %b) { ; CHECK-LABEL: test_vst1_f32 -; CHECK: st1 {v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* tail call void @llvm.arm.neon.vst1.v2f32(i8* %1, <2 x float> %b, i32 4) ret void @@ -857,7 +857,7 @@ define void @test_vst1_f32(float* %a, <2 x float> %b) { define void @test_vst1_f64(double* %a, <1 x double> %b) { ; CHECK-LABEL: test_vst1_f64 -; CHECK: st1 {v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* tail call void @llvm.arm.neon.vst1.v1f64(i8* %1, <1 x double> %b, i32 8) ret void @@ -865,7 +865,7 @@ define void @test_vst1_f64(double* %a, <1 x double> %b) { define void @test_vst2q_s8(i8* %a, [2 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst2q_s8 -; CHECK: st2 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %b.coerce, 1 tail call void @llvm.arm.neon.vst2.v16i8(i8* %a, <16 x i8> %b.coerce.fca.0.extract, <16 x i8> %b.coerce.fca.1.extract, i32 1) @@ -874,7 +874,7 @@ define void @test_vst2q_s8(i8* %a, [2 x <16 x i8>] %b.coerce) { define void @test_vst2q_s16(i16* %a, [2 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst2q_s16 -; CHECK: st2 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <8 x i16>] %b.coerce, 1 %1 = bitcast i16* %a to i8* @@ -884,7 +884,7 @@ define void @test_vst2q_s16(i16* %a, [2 x <8 x i16>] %b.coerce) { define void @test_vst2q_s32(i32* %a, [2 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst2q_s32 -; CHECK: st2 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %b.coerce, 1 %1 = bitcast i32* %a to i8* @@ -894,7 +894,7 @@ define void @test_vst2q_s32(i32* %a, [2 x <4 x i32>] %b.coerce) { define void @test_vst2q_s64(i64* %a, [2 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst2q_s64 -; CHECK: st2 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x i64>] %b.coerce, 1 %1 = bitcast i64* %a to i8* @@ -904,7 +904,7 @@ define void @test_vst2q_s64(i64* %a, [2 x <2 x i64>] %b.coerce) { define void @test_vst2q_f32(float* %a, [2 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vst2q_f32 -; CHECK: st2 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x float>] %b.coerce, 1 %1 = bitcast float* %a to i8* @@ -914,7 +914,7 @@ define void @test_vst2q_f32(float* %a, [2 x <4 x float>] %b.coerce) { define void @test_vst2q_f64(double* %a, [2 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vst2q_f64 -; CHECK: st2 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x double>] %b.coerce, 1 %1 = bitcast double* %a to i8* @@ -924,7 +924,7 @@ define void @test_vst2q_f64(double* %a, [2 x <2 x double>] %b.coerce) { define void @test_vst2_s8(i8* %a, [2 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst2_s8 -; CHECK: st2 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <8 x i8>] %b.coerce, 1 tail call void @llvm.arm.neon.vst2.v8i8(i8* %a, <8 x i8> %b.coerce.fca.0.extract, <8 x i8> %b.coerce.fca.1.extract, i32 1) @@ -933,7 +933,7 @@ define void @test_vst2_s8(i8* %a, [2 x <8 x i8>] %b.coerce) { define void @test_vst2_s16(i16* %a, [2 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst2_s16 -; CHECK: st2 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x i16>] %b.coerce, 1 %1 = bitcast i16* %a to i8* @@ -943,7 +943,7 @@ define void @test_vst2_s16(i16* %a, [2 x <4 x i16>] %b.coerce) { define void @test_vst2_s32(i32* %a, [2 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst2_s32 -; CHECK: st2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %b.coerce, 1 %1 = bitcast i32* %a to i8* @@ -953,7 +953,7 @@ define void @test_vst2_s32(i32* %a, [2 x <2 x i32>] %b.coerce) { define void @test_vst2_s64(i64* %a, [2 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst2_s64 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <1 x i64>] %b.coerce, 1 %1 = bitcast i64* %a to i8* @@ -963,7 +963,7 @@ define void @test_vst2_s64(i64* %a, [2 x <1 x i64>] %b.coerce) { define void @test_vst2_f32(float* %a, [2 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vst2_f32 -; CHECK: st2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x float>] %b.coerce, 1 %1 = bitcast float* %a to i8* @@ -973,7 +973,7 @@ define void @test_vst2_f32(float* %a, [2 x <2 x float>] %b.coerce) { define void @test_vst2_f64(double* %a, [2 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vst2_f64 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [2 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <1 x double>] %b.coerce, 1 %1 = bitcast double* %a to i8* @@ -983,7 +983,7 @@ define void @test_vst2_f64(double* %a, [2 x <1 x double>] %b.coerce) { define void @test_vst3q_s8(i8* %a, [3 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst3q_s8 -; CHECK: st3 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <16 x i8>] %b.coerce, 2 @@ -993,7 +993,7 @@ define void @test_vst3q_s8(i8* %a, [3 x <16 x i8>] %b.coerce) { define void @test_vst3q_s16(i16* %a, [3 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst3q_s16 -; CHECK: st3 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <8 x i16>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <8 x i16>] %b.coerce, 2 @@ -1004,7 +1004,7 @@ define void @test_vst3q_s16(i16* %a, [3 x <8 x i16>] %b.coerce) { define void @test_vst3q_s32(i32* %a, [3 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst3q_s32 -; CHECK: st3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x i32>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <4 x i32>] %b.coerce, 2 @@ -1015,7 +1015,7 @@ define void @test_vst3q_s32(i32* %a, [3 x <4 x i32>] %b.coerce) { define void @test_vst3q_s64(i64* %a, [3 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst3q_s64 -; CHECK: st3 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x i64>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <2 x i64>] %b.coerce, 2 @@ -1026,7 +1026,7 @@ define void @test_vst3q_s64(i64* %a, [3 x <2 x i64>] %b.coerce) { define void @test_vst3q_f32(float* %a, [3 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vst3q_f32 -; CHECK: st3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x float>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <4 x float>] %b.coerce, 2 @@ -1037,7 +1037,7 @@ define void @test_vst3q_f32(float* %a, [3 x <4 x float>] %b.coerce) { define void @test_vst3q_f64(double* %a, [3 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vst3q_f64 -; CHECK: st3 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x double>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <2 x double>] %b.coerce, 2 @@ -1048,7 +1048,7 @@ define void @test_vst3q_f64(double* %a, [3 x <2 x double>] %b.coerce) { define void @test_vst3_s8(i8* %a, [3 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst3_s8 -; CHECK: st3 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <8 x i8>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <8 x i8>] %b.coerce, 2 @@ -1058,7 +1058,7 @@ define void @test_vst3_s8(i8* %a, [3 x <8 x i8>] %b.coerce) { define void @test_vst3_s16(i16* %a, [3 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst3_s16 -; CHECK: st3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x i16>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <4 x i16>] %b.coerce, 2 @@ -1069,7 +1069,7 @@ define void @test_vst3_s16(i16* %a, [3 x <4 x i16>] %b.coerce) { define void @test_vst3_s32(i32* %a, [3 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst3_s32 -; CHECK: st3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x i32>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <2 x i32>] %b.coerce, 2 @@ -1080,7 +1080,7 @@ define void @test_vst3_s32(i32* %a, [3 x <2 x i32>] %b.coerce) { define void @test_vst3_s64(i64* %a, [3 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst3_s64 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <1 x i64>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <1 x i64>] %b.coerce, 2 @@ -1091,7 +1091,7 @@ define void @test_vst3_s64(i64* %a, [3 x <1 x i64>] %b.coerce) { define void @test_vst3_f32(float* %a, [3 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vst3_f32 -; CHECK: st3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st3 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x float>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <2 x float>] %b.coerce, 2 @@ -1102,7 +1102,7 @@ define void @test_vst3_f32(float* %a, [3 x <2 x float>] %b.coerce) { define void @test_vst3_f64(double* %a, [3 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vst3_f64 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [3 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <1 x double>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [3 x <1 x double>] %b.coerce, 2 @@ -1113,7 +1113,7 @@ define void @test_vst3_f64(double* %a, [3 x <1 x double>] %b.coerce) { define void @test_vst4q_s8(i8* %a, [4 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst4q_s8 -; CHECK: st4 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <16 x i8>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <16 x i8>] %b.coerce, 2 @@ -1124,7 +1124,7 @@ define void @test_vst4q_s8(i8* %a, [4 x <16 x i8>] %b.coerce) { define void @test_vst4q_s16(i16* %a, [4 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst4q_s16 -; CHECK: st4 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <8 x i16>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <8 x i16>] %b.coerce, 2 @@ -1136,7 +1136,7 @@ define void @test_vst4q_s16(i16* %a, [4 x <8 x i16>] %b.coerce) { define void @test_vst4q_s32(i32* %a, [4 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst4q_s32 -; CHECK: st4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x i32>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <4 x i32>] %b.coerce, 2 @@ -1148,7 +1148,7 @@ define void @test_vst4q_s32(i32* %a, [4 x <4 x i32>] %b.coerce) { define void @test_vst4q_s64(i64* %a, [4 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst4q_s64 -; CHECK: st4 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x i64>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <2 x i64>] %b.coerce, 2 @@ -1160,7 +1160,7 @@ define void @test_vst4q_s64(i64* %a, [4 x <2 x i64>] %b.coerce) { define void @test_vst4q_f32(float* %a, [4 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vst4q_f32 -; CHECK: st4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x float>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <4 x float>] %b.coerce, 2 @@ -1172,7 +1172,7 @@ define void @test_vst4q_f32(float* %a, [4 x <4 x float>] %b.coerce) { define void @test_vst4q_f64(double* %a, [4 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vst4q_f64 -; CHECK: st4 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x double>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <2 x double>] %b.coerce, 2 @@ -1184,7 +1184,7 @@ define void @test_vst4q_f64(double* %a, [4 x <2 x double>] %b.coerce) { define void @test_vst4_s8(i8* %a, [4 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst4_s8 -; CHECK: st4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <8 x i8>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <8 x i8>] %b.coerce, 2 @@ -1195,7 +1195,7 @@ define void @test_vst4_s8(i8* %a, [4 x <8 x i8>] %b.coerce) { define void @test_vst4_s16(i16* %a, [4 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst4_s16 -; CHECK: st4 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x i16>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <4 x i16>] %b.coerce, 2 @@ -1207,7 +1207,7 @@ define void @test_vst4_s16(i16* %a, [4 x <4 x i16>] %b.coerce) { define void @test_vst4_s32(i32* %a, [4 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst4_s32 -; CHECK: st4 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x i32>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <2 x i32>] %b.coerce, 2 @@ -1219,7 +1219,7 @@ define void @test_vst4_s32(i32* %a, [4 x <2 x i32>] %b.coerce) { define void @test_vst4_s64(i64* %a, [4 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst4_s64 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <1 x i64>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <1 x i64>] %b.coerce, 2 @@ -1231,7 +1231,7 @@ define void @test_vst4_s64(i64* %a, [4 x <1 x i64>] %b.coerce) { define void @test_vst4_f32(float* %a, [4 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vst4_f32 -; CHECK: st4 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st4 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x float>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <2 x float>] %b.coerce, 2 @@ -1243,7 +1243,7 @@ define void @test_vst4_f32(float* %a, [4 x <2 x float>] %b.coerce) { define void @test_vst4_f64(double* %a, [4 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vst4_f64 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %b.coerce.fca.0.extract = extractvalue [4 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <1 x double>] %b.coerce, 1 %b.coerce.fca.2.extract = extractvalue [4 x <1 x double>] %b.coerce, 2 @@ -1304,7 +1304,7 @@ declare void @llvm.arm.neon.vst4.v1f64(i8*, <1 x double>, <1 x double>, <1 x dou define %struct.int8x16x2_t @test_vld1q_s8_x2(i8* %a) { ; CHECK-LABEL: test_vld1q_s8_x2 -; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %1 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.vld1x2.v16i8(i8* %a, i32 1) %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0 %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1 @@ -1315,7 +1315,7 @@ define %struct.int8x16x2_t @test_vld1q_s8_x2(i8* %a) { define %struct.int16x8x2_t @test_vld1q_s16_x2(i16* %a) { ; CHECK-LABEL: test_vld1q_s16_x2 -; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x2.v8i16(i8* %1, i32 2) %3 = extractvalue { <8 x i16>, <8 x i16> } %2, 0 @@ -1327,7 +1327,7 @@ define %struct.int16x8x2_t @test_vld1q_s16_x2(i16* %a) { define %struct.int32x4x2_t @test_vld1q_s32_x2(i32* %a) { ; CHECK-LABEL: test_vld1q_s32_x2 -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.vld1x2.v4i32(i8* %1, i32 4) %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 0 @@ -1339,7 +1339,7 @@ define %struct.int32x4x2_t @test_vld1q_s32_x2(i32* %a) { define %struct.int64x2x2_t @test_vld1q_s64_x2(i64* %a) { ; CHECK-LABEL: test_vld1q_s64_x2 -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.vld1x2.v2i64(i8* %1, i32 8) %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 0 @@ -1351,7 +1351,7 @@ define %struct.int64x2x2_t @test_vld1q_s64_x2(i64* %a) { define %struct.float32x4x2_t @test_vld1q_f32_x2(float* %a) { ; CHECK-LABEL: test_vld1q_f32_x2 -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* %2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.vld1x2.v4f32(i8* %1, i32 4) %3 = extractvalue { <4 x float>, <4 x float> } %2, 0 @@ -1364,7 +1364,7 @@ define %struct.float32x4x2_t @test_vld1q_f32_x2(float* %a) { define %struct.float64x2x2_t @test_vld1q_f64_x2(double* %a) { ; CHECK-LABEL: test_vld1q_f64_x2 -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.vld1x2.v2f64(i8* %1, i32 8) %3 = extractvalue { <2 x double>, <2 x double> } %2, 0 @@ -1376,7 +1376,7 @@ define %struct.float64x2x2_t @test_vld1q_f64_x2(double* %a) { define %struct.int8x8x2_t @test_vld1_s8_x2(i8* %a) { ; CHECK-LABEL: test_vld1_s8_x2 -; CHECK: ld1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %1 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.vld1x2.v8i8(i8* %a, i32 1) %2 = extractvalue { <8 x i8>, <8 x i8> } %1, 0 %3 = extractvalue { <8 x i8>, <8 x i8> } %1, 1 @@ -1387,7 +1387,7 @@ define %struct.int8x8x2_t @test_vld1_s8_x2(i8* %a) { define %struct.int16x4x2_t @test_vld1_s16_x2(i16* %a) { ; CHECK-LABEL: test_vld1_s16_x2 -; CHECK: ld1 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.vld1x2.v4i16(i8* %1, i32 2) %3 = extractvalue { <4 x i16>, <4 x i16> } %2, 0 @@ -1399,7 +1399,7 @@ define %struct.int16x4x2_t @test_vld1_s16_x2(i16* %a) { define %struct.int32x2x2_t @test_vld1_s32_x2(i32* %a) { ; CHECK-LABEL: test_vld1_s32_x2 -; CHECK: ld1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.vld1x2.v2i32(i8* %1, i32 4) %3 = extractvalue { <2 x i32>, <2 x i32> } %2, 0 @@ -1411,7 +1411,7 @@ define %struct.int32x2x2_t @test_vld1_s32_x2(i32* %a) { define %struct.int64x1x2_t @test_vld1_s64_x2(i64* %a) { ; CHECK-LABEL: test_vld1_s64_x2 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.vld1x2.v1i64(i8* %1, i32 8) %3 = extractvalue { <1 x i64>, <1 x i64> } %2, 0 @@ -1423,7 +1423,7 @@ define %struct.int64x1x2_t @test_vld1_s64_x2(i64* %a) { define %struct.float32x2x2_t @test_vld1_f32_x2(float* %a) { ; CHECK-LABEL: test_vld1_f32_x2 -; CHECK: ld1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* %2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.vld1x2.v2f32(i8* %1, i32 4) %3 = extractvalue { <2 x float>, <2 x float> } %2, 0 @@ -1435,7 +1435,7 @@ define %struct.float32x2x2_t @test_vld1_f32_x2(float* %a) { define %struct.float64x1x2_t @test_vld1_f64_x2(double* %a) { ; CHECK-LABEL: test_vld1_f64_x2 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.vld1x2.v1f64(i8* %1, i32 8) %3 = extractvalue { <1 x double>, <1 x double> } %2, 0 @@ -1447,7 +1447,7 @@ define %struct.float64x1x2_t @test_vld1_f64_x2(double* %a) { define %struct.int8x16x3_t @test_vld1q_s8_x3(i8* %a) { ; CHECK-LABEL: test_vld1q_s8_x3 -; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, +; CHECK: ld1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, ; [{{x[0-9]+|sp}}] %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.vld1x3.v16i8(i8* %a, i32 1) %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 @@ -1461,7 +1461,7 @@ define %struct.int8x16x3_t @test_vld1q_s8_x3(i8* %a) { define %struct.int16x8x3_t @test_vld1q_s16_x3(i16* %a) { ; CHECK-LABEL: test_vld1q_s16_x3 -; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, +; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, ; [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %2 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x3.v8i16(i8* %1, i32 2) @@ -1476,7 +1476,7 @@ define %struct.int16x8x3_t @test_vld1q_s16_x3(i16* %a) { define %struct.int32x4x3_t @test_vld1q_s32_x3(i32* %a) { ; CHECK-LABEL: test_vld1q_s32_x3 -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, ; [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %2 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.vld1x3.v4i32(i8* %1, i32 4) @@ -1491,7 +1491,7 @@ define %struct.int32x4x3_t @test_vld1q_s32_x3(i32* %a) { define %struct.int64x2x3_t @test_vld1q_s64_x3(i64* %a) { ; CHECK-LABEL: test_vld1q_s64_x3 -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, ; [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %2 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.vld1x3.v2i64(i8* %1, i32 8) @@ -1506,7 +1506,7 @@ define %struct.int64x2x3_t @test_vld1q_s64_x3(i64* %a) { define %struct.float32x4x3_t @test_vld1q_f32_x3(float* %a) { ; CHECK-LABEL: test_vld1q_f32_x3 -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, ; [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* %2 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.vld1x3.v4f32(i8* %1, i32 4) @@ -1522,7 +1522,7 @@ define %struct.float32x4x3_t @test_vld1q_f32_x3(float* %a) { define %struct.float64x2x3_t @test_vld1q_f64_x3(double* %a) { ; CHECK-LABEL: test_vld1q_f64_x3 -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, ; [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %2 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.vld1x3.v2f64(i8* %1, i32 8) @@ -1537,7 +1537,7 @@ define %struct.float64x2x3_t @test_vld1q_f64_x3(double* %a) { define %struct.int8x8x3_t @test_vld1_s8_x3(i8* %a) { ; CHECK-LABEL: test_vld1_s8_x3 -; CHECK: ld1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, +; CHECK: ld1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, ; [{{x[0-9]+|sp}}] %1 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.vld1x3.v8i8(i8* %a, i32 1) %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %1, 0 @@ -1551,7 +1551,7 @@ define %struct.int8x8x3_t @test_vld1_s8_x3(i8* %a) { define %struct.int16x4x3_t @test_vld1_s16_x3(i16* %a) { ; CHECK-LABEL: test_vld1_s16_x3 -; CHECK: ld1 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, +; CHECK: ld1 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, ; [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %2 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.vld1x3.v4i16(i8* %1, i32 2) @@ -1567,7 +1567,7 @@ define %struct.int16x4x3_t @test_vld1_s16_x3(i16* %a) { define %struct.int32x2x3_t @test_vld1_s32_x3(i32* %a) { %1 = bitcast i32* %a to i8* ; CHECK-LABEL: test_vld1_s32_x3 -; CHECK: ld1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, +; CHECK: ld1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, ; [{{x[0-9]+|sp}}] %2 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.vld1x3.v2i32(i8* %1, i32 4) %3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %2, 0 @@ -1581,7 +1581,7 @@ define %struct.int32x2x3_t @test_vld1_s32_x3(i32* %a) { define %struct.int64x1x3_t @test_vld1_s64_x3(i64* %a) { ; CHECK-LABEL: test_vld1_s64_x3 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, ; [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %2 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.vld1x3.v1i64(i8* %1, i32 8) @@ -1596,7 +1596,7 @@ define %struct.int64x1x3_t @test_vld1_s64_x3(i64* %a) { define %struct.float32x2x3_t @test_vld1_f32_x3(float* %a) { ; CHECK-LABEL: test_vld1_f32_x3 -; CHECK: ld1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, +; CHECK: ld1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, ; [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* %2 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.vld1x3.v2f32(i8* %1, i32 4) @@ -1612,7 +1612,7 @@ define %struct.float32x2x3_t @test_vld1_f32_x3(float* %a) { define %struct.float64x1x3_t @test_vld1_f64_x3(double* %a) { ; CHECK-LABEL: test_vld1_f64_x3 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, ; [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %2 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.vld1x3.v1f64(i8* %1, i32 8) @@ -1627,8 +1627,8 @@ define %struct.float64x1x3_t @test_vld1_f64_x3(double* %a) { define %struct.int8x16x4_t @test_vld1q_s8_x4(i8* %a) { ; CHECK-LABEL: test_vld1q_s8_x4 -; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, -; v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, +; v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.vld1x4.v16i8(i8* %a, i32 1) %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1 @@ -1643,8 +1643,8 @@ define %struct.int8x16x4_t @test_vld1q_s8_x4(i8* %a) { define %struct.int16x8x4_t @test_vld1q_s16_x4(i16* %a) { ; CHECK-LABEL: test_vld1q_s16_x4 -; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, -; v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, +; v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %2 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x4.v8i16(i8* %1, i32 2) %3 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %2, 0 @@ -1660,8 +1660,8 @@ define %struct.int16x8x4_t @test_vld1q_s16_x4(i16* %a) { define %struct.int32x4x4_t @test_vld1q_s32_x4(i32* %a) { ; CHECK-LABEL: test_vld1q_s32_x4 -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, -; v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, +; v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %2 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.vld1x4.v4i32(i8* %1, i32 4) %3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %2, 0 @@ -1677,8 +1677,8 @@ define %struct.int32x4x4_t @test_vld1q_s32_x4(i32* %a) { define %struct.int64x2x4_t @test_vld1q_s64_x4(i64* %a) { ; CHECK-LABEL: test_vld1q_s64_x4 -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, -; v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, +; v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %2 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.vld1x4.v2i64(i8* %1, i32 8) %3 = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %2, 0 @@ -1694,8 +1694,8 @@ define %struct.int64x2x4_t @test_vld1q_s64_x4(i64* %a) { define %struct.float32x4x4_t @test_vld1q_f32_x4(float* %a) { ; CHECK-LABEL: test_vld1q_f32_x4 -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, -; v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, +; v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.vld1x4.v4f32(i8* %1, i32 4) %3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0 @@ -1711,8 +1711,8 @@ define %struct.float32x4x4_t @test_vld1q_f32_x4(float* %a) { define %struct.float64x2x4_t @test_vld1q_f64_x4(double* %a) { ; CHECK-LABEL: test_vld1q_f64_x4 -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, -; v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, +; v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %2 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.vld1x4.v2f64(i8* %1, i32 8) %3 = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %2, 0 @@ -1728,8 +1728,8 @@ define %struct.float64x2x4_t @test_vld1q_f64_x4(double* %a) { define %struct.int8x8x4_t @test_vld1_s8_x4(i8* %a) { ; CHECK-LABEL: test_vld1_s8_x4 -; CHECK: ld1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, -; v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, +; v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %1 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.vld1x4.v8i8(i8* %a, i32 1) %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0 %3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 1 @@ -1744,8 +1744,8 @@ define %struct.int8x8x4_t @test_vld1_s8_x4(i8* %a) { define %struct.int16x4x4_t @test_vld1_s16_x4(i16* %a) { ; CHECK-LABEL: test_vld1_s16_x4 -; CHECK: ld1 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, -; v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, +; v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %1 = bitcast i16* %a to i8* %2 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.vld1x4.v4i16(i8* %1, i32 2) %3 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %2, 0 @@ -1761,8 +1761,8 @@ define %struct.int16x4x4_t @test_vld1_s16_x4(i16* %a) { define %struct.int32x2x4_t @test_vld1_s32_x4(i32* %a) { ; CHECK-LABEL: test_vld1_s32_x4 -; CHECK: ld1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, -; v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, +; v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = bitcast i32* %a to i8* %2 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.vld1x4.v2i32(i8* %1, i32 4) %3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %2, 0 @@ -1778,8 +1778,8 @@ define %struct.int32x2x4_t @test_vld1_s32_x4(i32* %a) { define %struct.int64x1x4_t @test_vld1_s64_x4(i64* %a) { ; CHECK-LABEL: test_vld1_s64_x4 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, -; v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, +; v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = bitcast i64* %a to i8* %2 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.vld1x4.v1i64(i8* %1, i32 8) %3 = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %2, 0 @@ -1795,8 +1795,8 @@ define %struct.int64x1x4_t @test_vld1_s64_x4(i64* %a) { define %struct.float32x2x4_t @test_vld1_f32_x4(float* %a) { ; CHECK-LABEL: test_vld1_f32_x4 -; CHECK: ld1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, -; v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, +; v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = bitcast float* %a to i8* %2 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.vld1x4.v2f32(i8* %1, i32 4) %3 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %2, 0 @@ -1813,8 +1813,8 @@ define %struct.float32x2x4_t @test_vld1_f32_x4(float* %a) { define %struct.float64x1x4_t @test_vld1_f64_x4(double* %a) { ; CHECK-LABEL: test_vld1_f64_x4 -; CHECK: ld1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, -; v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: ld1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, +; v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = bitcast double* %a to i8* %2 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.vld1x4.v1f64(i8* %1, i32 8) %3 = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %2, 0 @@ -1830,7 +1830,7 @@ define %struct.float64x1x4_t @test_vld1_f64_x4(double* %a) { define void @test_vst1q_s8_x2(i8* %a, [2 x <16 x i8>] %b) { ; CHECK-LABEL: test_vst1q_s8_x2 -; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <16 x i8>] %b, 0 %2 = extractvalue [2 x <16 x i8>] %b, 1 tail call void @llvm.aarch64.neon.vst1x2.v16i8(i8* %a, <16 x i8> %1, <16 x i8> %2, i32 1) @@ -1839,7 +1839,7 @@ define void @test_vst1q_s8_x2(i8* %a, [2 x <16 x i8>] %b) { define void @test_vst1q_s16_x2(i16* %a, [2 x <8 x i16>] %b) { ; CHECK-LABEL: test_vst1q_s16_x2 -; CHECK: st1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <8 x i16>] %b, 0 %2 = extractvalue [2 x <8 x i16>] %b, 1 %3 = bitcast i16* %a to i8* @@ -1849,7 +1849,7 @@ define void @test_vst1q_s16_x2(i16* %a, [2 x <8 x i16>] %b) { define void @test_vst1q_s32_x2(i32* %a, [2 x <4 x i32>] %b) { ; CHECK-LABEL: test_vst1q_s32_x2 -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <4 x i32>] %b, 0 %2 = extractvalue [2 x <4 x i32>] %b, 1 %3 = bitcast i32* %a to i8* @@ -1859,7 +1859,7 @@ define void @test_vst1q_s32_x2(i32* %a, [2 x <4 x i32>] %b) { define void @test_vst1q_s64_x2(i64* %a, [2 x <2 x i64>] %b) { ; CHECK-LABEL: test_vst1q_s64_x2 -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <2 x i64>] %b, 0 %2 = extractvalue [2 x <2 x i64>] %b, 1 %3 = bitcast i64* %a to i8* @@ -1869,7 +1869,7 @@ define void @test_vst1q_s64_x2(i64* %a, [2 x <2 x i64>] %b) { define void @test_vst1q_f32_x2(float* %a, [2 x <4 x float>] %b) { ; CHECK-LABEL: test_vst1q_f32_x2 -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <4 x float>] %b, 0 %2 = extractvalue [2 x <4 x float>] %b, 1 %3 = bitcast float* %a to i8* @@ -1880,7 +1880,7 @@ define void @test_vst1q_f32_x2(float* %a, [2 x <4 x float>] %b) { define void @test_vst1q_f64_x2(double* %a, [2 x <2 x double>] %b) { ; CHECK-LABEL: test_vst1q_f64_x2 -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <2 x double>] %b, 0 %2 = extractvalue [2 x <2 x double>] %b, 1 %3 = bitcast double* %a to i8* @@ -1890,7 +1890,7 @@ define void @test_vst1q_f64_x2(double* %a, [2 x <2 x double>] %b) { define void @test_vst1_s8_x2(i8* %a, [2 x <8 x i8>] %b) { ; CHECK-LABEL: test_vst1_s8_x2 -; CHECK: st1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <8 x i8>] %b, 0 %2 = extractvalue [2 x <8 x i8>] %b, 1 tail call void @llvm.aarch64.neon.vst1x2.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 1) @@ -1899,7 +1899,7 @@ define void @test_vst1_s8_x2(i8* %a, [2 x <8 x i8>] %b) { define void @test_vst1_s16_x2(i16* %a, [2 x <4 x i16>] %b) { ; CHECK-LABEL: test_vst1_s16_x2 -; CHECK: st1 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <4 x i16>] %b, 0 %2 = extractvalue [2 x <4 x i16>] %b, 1 %3 = bitcast i16* %a to i8* @@ -1909,7 +1909,7 @@ define void @test_vst1_s16_x2(i16* %a, [2 x <4 x i16>] %b) { define void @test_vst1_s32_x2(i32* %a, [2 x <2 x i32>] %b) { ; CHECK-LABEL: test_vst1_s32_x2 -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <2 x i32>] %b, 0 %2 = extractvalue [2 x <2 x i32>] %b, 1 %3 = bitcast i32* %a to i8* @@ -1919,7 +1919,7 @@ define void @test_vst1_s32_x2(i32* %a, [2 x <2 x i32>] %b) { define void @test_vst1_s64_x2(i64* %a, [2 x <1 x i64>] %b) { ; CHECK-LABEL: test_vst1_s64_x2 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <1 x i64>] %b, 0 %2 = extractvalue [2 x <1 x i64>] %b, 1 %3 = bitcast i64* %a to i8* @@ -1929,7 +1929,7 @@ define void @test_vst1_s64_x2(i64* %a, [2 x <1 x i64>] %b) { define void @test_vst1_f32_x2(float* %a, [2 x <2 x float>] %b) { ; CHECK-LABEL: test_vst1_f32_x2 -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <2 x float>] %b, 0 %2 = extractvalue [2 x <2 x float>] %b, 1 %3 = bitcast float* %a to i8* @@ -1939,7 +1939,7 @@ define void @test_vst1_f32_x2(float* %a, [2 x <2 x float>] %b) { define void @test_vst1_f64_x2(double* %a, [2 x <1 x double>] %b) { ; CHECK-LABEL: test_vst1_f64_x2 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = extractvalue [2 x <1 x double>] %b, 0 %2 = extractvalue [2 x <1 x double>] %b, 1 %3 = bitcast double* %a to i8* @@ -1949,7 +1949,7 @@ define void @test_vst1_f64_x2(double* %a, [2 x <1 x double>] %b) { define void @test_vst1q_s8_x3(i8* %a, [3 x <16 x i8>] %b) { ; CHECK-LABEL: test_vst1q_s8_x3 -; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, +; CHECK: st1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <16 x i8>] %b, 0 %2 = extractvalue [3 x <16 x i8>] %b, 1 @@ -1960,7 +1960,7 @@ define void @test_vst1q_s8_x3(i8* %a, [3 x <16 x i8>] %b) { define void @test_vst1q_s16_x3(i16* %a, [3 x <8 x i16>] %b) { ; CHECK-LABEL: test_vst1q_s16_x3 -; CHECK: st1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, +; CHECK: st1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <8 x i16>] %b, 0 %2 = extractvalue [3 x <8 x i16>] %b, 1 @@ -1972,7 +1972,7 @@ define void @test_vst1q_s16_x3(i16* %a, [3 x <8 x i16>] %b) { define void @test_vst1q_s32_x3(i32* %a, [3 x <4 x i32>] %b) { ; CHECK-LABEL: test_vst1q_s32_x3 -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <4 x i32>] %b, 0 %2 = extractvalue [3 x <4 x i32>] %b, 1 @@ -1984,7 +1984,7 @@ define void @test_vst1q_s32_x3(i32* %a, [3 x <4 x i32>] %b) { define void @test_vst1q_s64_x3(i64* %a, [3 x <2 x i64>] %b) { ; CHECK-LABEL: test_vst1q_s64_x3 -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <2 x i64>] %b, 0 %2 = extractvalue [3 x <2 x i64>] %b, 1 @@ -1996,7 +1996,7 @@ define void @test_vst1q_s64_x3(i64* %a, [3 x <2 x i64>] %b) { define void @test_vst1q_f32_x3(float* %a, [3 x <4 x float>] %b) { ; CHECK-LABEL: test_vst1q_f32_x3 -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <4 x float>] %b, 0 %2 = extractvalue [3 x <4 x float>] %b, 1 @@ -2008,7 +2008,7 @@ define void @test_vst1q_f32_x3(float* %a, [3 x <4 x float>] %b) { define void @test_vst1q_f64_x3(double* %a, [3 x <2 x double>] %b) { ; CHECK-LABEL: test_vst1q_f64_x3 -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <2 x double>] %b, 0 %2 = extractvalue [3 x <2 x double>] %b, 1 @@ -2020,7 +2020,7 @@ define void @test_vst1q_f64_x3(double* %a, [3 x <2 x double>] %b) { define void @test_vst1_s8_x3(i8* %a, [3 x <8 x i8>] %b) { ; CHECK-LABEL: test_vst1_s8_x3 -; CHECK: st1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, +; CHECK: st1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <8 x i8>] %b, 0 %2 = extractvalue [3 x <8 x i8>] %b, 1 @@ -2031,7 +2031,7 @@ define void @test_vst1_s8_x3(i8* %a, [3 x <8 x i8>] %b) { define void @test_vst1_s16_x3(i16* %a, [3 x <4 x i16>] %b) { ; CHECK-LABEL: test_vst1_s16_x3 -; CHECK: st1 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, +; CHECK: st1 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <4 x i16>] %b, 0 %2 = extractvalue [3 x <4 x i16>] %b, 1 @@ -2043,7 +2043,7 @@ define void @test_vst1_s16_x3(i16* %a, [3 x <4 x i16>] %b) { define void @test_vst1_s32_x3(i32* %a, [3 x <2 x i32>] %b) { ; CHECK-LABEL: test_vst1_s32_x3 -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <2 x i32>] %b, 0 %2 = extractvalue [3 x <2 x i32>] %b, 1 @@ -2055,7 +2055,7 @@ define void @test_vst1_s32_x3(i32* %a, [3 x <2 x i32>] %b) { define void @test_vst1_s64_x3(i64* %a, [3 x <1 x i64>] %b) { ; CHECK-LABEL: test_vst1_s64_x3 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <1 x i64>] %b, 0 %2 = extractvalue [3 x <1 x i64>] %b, 1 @@ -2067,7 +2067,7 @@ define void @test_vst1_s64_x3(i64* %a, [3 x <1 x i64>] %b) { define void @test_vst1_f32_x3(float* %a, [3 x <2 x float>] %b) { ; CHECK-LABEL: test_vst1_f32_x3 -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <2 x float>] %b, 0 %2 = extractvalue [3 x <2 x float>] %b, 1 @@ -2079,7 +2079,7 @@ define void @test_vst1_f32_x3(float* %a, [3 x <2 x float>] %b) { define void @test_vst1_f64_x3(double* %a, [3 x <1 x double>] %b) { ; CHECK-LABEL: test_vst1_f64_x3 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, ; [{{x[0-9]+|sp}}] %1 = extractvalue [3 x <1 x double>] %b, 0 %2 = extractvalue [3 x <1 x double>] %b, 1 @@ -2091,8 +2091,8 @@ define void @test_vst1_f64_x3(double* %a, [3 x <1 x double>] %b) { define void @test_vst1q_s8_x4(i8* %a, [4 x <16 x i8>] %b) { ; CHECK-LABEL: test_vst1q_s8_x4 -; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, -; v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, +; v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <16 x i8>] %b, 0 %2 = extractvalue [4 x <16 x i8>] %b, 1 %3 = extractvalue [4 x <16 x i8>] %b, 2 @@ -2103,8 +2103,8 @@ define void @test_vst1q_s8_x4(i8* %a, [4 x <16 x i8>] %b) { define void @test_vst1q_s16_x4(i16* %a, [4 x <8 x i16>] %b) { ; CHECK-LABEL: test_vst1q_s16_x4 -; CHECK: st1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, -; v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, +; v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <8 x i16>] %b, 0 %2 = extractvalue [4 x <8 x i16>] %b, 1 %3 = extractvalue [4 x <8 x i16>] %b, 2 @@ -2116,8 +2116,8 @@ define void @test_vst1q_s16_x4(i16* %a, [4 x <8 x i16>] %b) { define void @test_vst1q_s32_x4(i32* %a, [4 x <4 x i32>] %b) { ; CHECK-LABEL: test_vst1q_s32_x4 -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, -; v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, +; v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <4 x i32>] %b, 0 %2 = extractvalue [4 x <4 x i32>] %b, 1 %3 = extractvalue [4 x <4 x i32>] %b, 2 @@ -2129,8 +2129,8 @@ define void @test_vst1q_s32_x4(i32* %a, [4 x <4 x i32>] %b) { define void @test_vst1q_s64_x4(i64* %a, [4 x <2 x i64>] %b) { ; CHECK-LABEL: test_vst1q_s64_x4 -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, -; v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, +; v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <2 x i64>] %b, 0 %2 = extractvalue [4 x <2 x i64>] %b, 1 %3 = extractvalue [4 x <2 x i64>] %b, 2 @@ -2142,8 +2142,8 @@ define void @test_vst1q_s64_x4(i64* %a, [4 x <2 x i64>] %b) { define void @test_vst1q_f32_x4(float* %a, [4 x <4 x float>] %b) { ; CHECK-LABEL: test_vst1q_f32_x4 -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, -; v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, +; v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <4 x float>] %b, 0 %2 = extractvalue [4 x <4 x float>] %b, 1 %3 = extractvalue [4 x <4 x float>] %b, 2 @@ -2155,8 +2155,8 @@ define void @test_vst1q_f32_x4(float* %a, [4 x <4 x float>] %b) { define void @test_vst1q_f64_x4(double* %a, [4 x <2 x double>] %b) { ; CHECK-LABEL: test_vst1q_f64_x4 -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, -; v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, +; v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <2 x double>] %b, 0 %2 = extractvalue [4 x <2 x double>] %b, 1 %3 = extractvalue [4 x <2 x double>] %b, 2 @@ -2168,8 +2168,8 @@ define void @test_vst1q_f64_x4(double* %a, [4 x <2 x double>] %b) { define void @test_vst1_s8_x4(i8* %a, [4 x <8 x i8>] %b) { ; CHECK-LABEL: test_vst1_s8_x4 -; CHECK: st1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, -; v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, +; v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <8 x i8>] %b, 0 %2 = extractvalue [4 x <8 x i8>] %b, 1 %3 = extractvalue [4 x <8 x i8>] %b, 2 @@ -2180,8 +2180,8 @@ define void @test_vst1_s8_x4(i8* %a, [4 x <8 x i8>] %b) { define void @test_vst1_s16_x4(i16* %a, [4 x <4 x i16>] %b) { ; CHECK-LABEL: test_vst1_s16_x4 -; CHECK: st1 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, -; v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, +; v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <4 x i16>] %b, 0 %2 = extractvalue [4 x <4 x i16>] %b, 1 %3 = extractvalue [4 x <4 x i16>] %b, 2 @@ -2193,8 +2193,8 @@ define void @test_vst1_s16_x4(i16* %a, [4 x <4 x i16>] %b) { define void @test_vst1_s32_x4(i32* %a, [4 x <2 x i32>] %b) { ; CHECK-LABEL: test_vst1_s32_x4 -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, -; v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, +; v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <2 x i32>] %b, 0 %2 = extractvalue [4 x <2 x i32>] %b, 1 %3 = extractvalue [4 x <2 x i32>] %b, 2 @@ -2206,8 +2206,8 @@ define void @test_vst1_s32_x4(i32* %a, [4 x <2 x i32>] %b) { define void @test_vst1_s64_x4(i64* %a, [4 x <1 x i64>] %b) { ; CHECK-LABEL: test_vst1_s64_x4 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, -; v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, +; v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <1 x i64>] %b, 0 %2 = extractvalue [4 x <1 x i64>] %b, 1 %3 = extractvalue [4 x <1 x i64>] %b, 2 @@ -2219,8 +2219,8 @@ define void @test_vst1_s64_x4(i64* %a, [4 x <1 x i64>] %b) { define void @test_vst1_f32_x4(float* %a, [4 x <2 x float>] %b) { ; CHECK-LABEL: test_vst1_f32_x4 -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, -; v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, +; v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <2 x float>] %b, 0 %2 = extractvalue [4 x <2 x float>] %b, 1 %3 = extractvalue [4 x <2 x float>] %b, 2 @@ -2232,8 +2232,8 @@ define void @test_vst1_f32_x4(float* %a, [4 x <2 x float>] %b) { define void @test_vst1_f64_x4(double* %a, [4 x <1 x double>] %b) { ; CHECK-LABEL: test_vst1_f64_x4 -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, -; v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}] +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, +; v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}] %1 = extractvalue [4 x <1 x double>] %b, 0 %2 = extractvalue [4 x <1 x double>] %b, 1 %3 = extractvalue [4 x <1 x double>] %b, 2 diff --git a/test/CodeGen/AArch64/neon-simd-ldst-one.ll b/test/CodeGen/AArch64/neon-simd-ldst-one.ll index 0ec5876325..75c2a82ab5 100644 --- a/test/CodeGen/AArch64/neon-simd-ldst-one.ll +++ b/test/CodeGen/AArch64/neon-simd-ldst-one.ll @@ -124,7 +124,7 @@ entry: define <16 x i8> @test_vld1q_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld1q_dup_s8 -; CHECK: ld1r {{{v[0-9]+}}.16b}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.16b }, [x0] entry: %0 = load i8* %a, align 1 %1 = insertelement <16 x i8> undef, i8 %0, i32 0 @@ -134,7 +134,7 @@ entry: define <8 x i16> @test_vld1q_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld1q_dup_s16 -; CHECK: ld1r {{{v[0-9]+}}.8h}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.8h }, [x0] entry: %0 = load i16* %a, align 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 0 @@ -144,7 +144,7 @@ entry: define <4 x i32> @test_vld1q_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld1q_dup_s32 -; CHECK: ld1r {{{v[0-9]+}}.4s}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.4s }, [x0] entry: %0 = load i32* %a, align 4 %1 = insertelement <4 x i32> undef, i32 %0, i32 0 @@ -154,7 +154,7 @@ entry: define <2 x i64> @test_vld1q_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld1q_dup_s64 -; CHECK: ld1r {{{v[0-9]+}}.2d}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.2d }, [x0] entry: %0 = load i64* %a, align 8 %1 = insertelement <2 x i64> undef, i64 %0, i32 0 @@ -164,7 +164,7 @@ entry: define <4 x float> @test_vld1q_dup_f32(float* %a) { ; CHECK-LABEL: test_vld1q_dup_f32 -; CHECK: ld1r {{{v[0-9]+}}.4s}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.4s }, [x0] entry: %0 = load float* %a, align 4 %1 = insertelement <4 x float> undef, float %0, i32 0 @@ -174,7 +174,7 @@ entry: define <2 x double> @test_vld1q_dup_f64(double* %a) { ; CHECK-LABEL: test_vld1q_dup_f64 -; CHECK: ld1r {{{v[0-9]+}}.2d}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.2d }, [x0] entry: %0 = load double* %a, align 8 %1 = insertelement <2 x double> undef, double %0, i32 0 @@ -184,7 +184,7 @@ entry: define <8 x i8> @test_vld1_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld1_dup_s8 -; CHECK: ld1r {{{v[0-9]+}}.8b}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.8b }, [x0] entry: %0 = load i8* %a, align 1 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 @@ -194,7 +194,7 @@ entry: define <4 x i16> @test_vld1_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld1_dup_s16 -; CHECK: ld1r {{{v[0-9]+}}.4h}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.4h }, [x0] entry: %0 = load i16* %a, align 2 %1 = insertelement <4 x i16> undef, i16 %0, i32 0 @@ -204,7 +204,7 @@ entry: define <2 x i32> @test_vld1_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld1_dup_s32 -; CHECK: ld1r {{{v[0-9]+}}.2s}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.2s }, [x0] entry: %0 = load i32* %a, align 4 %1 = insertelement <2 x i32> undef, i32 %0, i32 0 @@ -214,7 +214,7 @@ entry: define <1 x i64> @test_vld1_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld1_dup_s64 -; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0] entry: %0 = load i64* %a, align 8 %1 = insertelement <1 x i64> undef, i64 %0, i32 0 @@ -223,7 +223,7 @@ entry: define <2 x float> @test_vld1_dup_f32(float* %a) { ; CHECK-LABEL: test_vld1_dup_f32 -; CHECK: ld1r {{{v[0-9]+}}.2s}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.2s }, [x0] entry: %0 = load float* %a, align 4 %1 = insertelement <2 x float> undef, float %0, i32 0 @@ -233,7 +233,7 @@ entry: define <1 x double> @test_vld1_dup_f64(double* %a) { ; CHECK-LABEL: test_vld1_dup_f64 -; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0] entry: %0 = load double* %a, align 8 %1 = insertelement <1 x double> undef, double %0, i32 0 @@ -267,7 +267,7 @@ define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 { define %struct.int8x16x2_t @test_vld2q_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld2q_dup_s8 -; CHECK: ld2r {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, [x0] entry: %vld_dup = tail call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1) %0 = extractvalue { <16 x i8>, <16 x i8> } %vld_dup, 0 @@ -281,7 +281,7 @@ entry: define %struct.int16x8x2_t @test_vld2q_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld2q_dup_s16 -; CHECK: ld2r {{{v[0-9]+}}.8h, {{v[0-9]+}}.8h}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.8h, {{v[0-9]+}}.8h }, [x0] entry: %0 = bitcast i16* %a to i8* %vld_dup = tail call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2lane.v8i16(i8* %0, <8 x i16> undef, <8 x i16> undef, i32 0, i32 2) @@ -296,7 +296,7 @@ entry: define %struct.int32x4x2_t @test_vld2q_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld2q_dup_s32 -; CHECK: ld2r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0] entry: %0 = bitcast i32* %a to i8* %vld_dup = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %0, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4) @@ -311,7 +311,7 @@ entry: define %struct.int64x2x2_t @test_vld2q_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld2q_dup_s64 -; CHECK: ld2r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0] entry: %0 = bitcast i64* %a to i8* %vld_dup = tail call { <2 x i64>, <2 x i64> } @llvm.arm.neon.vld2lane.v2i64(i8* %0, <2 x i64> undef, <2 x i64> undef, i32 0, i32 8) @@ -326,7 +326,7 @@ entry: define %struct.float32x4x2_t @test_vld2q_dup_f32(float* %a) { ; CHECK-LABEL: test_vld2q_dup_f32 -; CHECK: ld2r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0] entry: %0 = bitcast float* %a to i8* %vld_dup = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2lane.v4f32(i8* %0, <4 x float> undef, <4 x float> undef, i32 0, i32 4) @@ -341,7 +341,7 @@ entry: define %struct.float64x2x2_t @test_vld2q_dup_f64(double* %a) { ; CHECK-LABEL: test_vld2q_dup_f64 -; CHECK: ld2r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0] entry: %0 = bitcast double* %a to i8* %vld_dup = tail call { <2 x double>, <2 x double> } @llvm.arm.neon.vld2lane.v2f64(i8* %0, <2 x double> undef, <2 x double> undef, i32 0, i32 8) @@ -356,7 +356,7 @@ entry: define %struct.int8x8x2_t @test_vld2_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld2_dup_s8 -; CHECK: ld2r {{{v[0-9]+}}.8b, {{v[0-9]+}}.8b}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.8b, {{v[0-9]+}}.8b }, [x0] entry: %vld_dup = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) %0 = extractvalue { <8 x i8>, <8 x i8> } %vld_dup, 0 @@ -370,7 +370,7 @@ entry: define %struct.int16x4x2_t @test_vld2_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld2_dup_s16 -; CHECK: ld2r {{{v[0-9]+}}.4h, {{v[0-9]+}}.4h}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.4h, {{v[0-9]+}}.4h }, [x0] entry: %0 = bitcast i16* %a to i8* %vld_dup = tail call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld2lane.v4i16(i8* %0, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) @@ -385,7 +385,7 @@ entry: define %struct.int32x2x2_t @test_vld2_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld2_dup_s32 -; CHECK: ld2r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0] entry: %0 = bitcast i32* %a to i8* %vld_dup = tail call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2lane.v2i32(i8* %0, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4) @@ -400,7 +400,7 @@ entry: define %struct.int64x1x2_t @test_vld2_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld2_dup_s64 -; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0] +; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0] entry: %0 = bitcast i64* %a to i8* %vld_dup = tail call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld2.v1i64(i8* %0, i32 8) @@ -413,7 +413,7 @@ entry: define %struct.float32x2x2_t @test_vld2_dup_f32(float* %a) { ; CHECK-LABEL: test_vld2_dup_f32 -; CHECK: ld2r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0] +; CHECK: ld2r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0] entry: %0 = bitcast float* %a to i8* %vld_dup = tail call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2lane.v2f32(i8* %0, <2 x float> undef, <2 x float> undef, i32 0, i32 4) @@ -428,7 +428,7 @@ entry: define %struct.float64x1x2_t @test_vld2_dup_f64(double* %a) { ; CHECK-LABEL: test_vld2_dup_f64 -; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0] +; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0] entry: %0 = bitcast double* %a to i8* %vld_dup = tail call { <1 x double>, <1 x double> } @llvm.arm.neon.vld2.v1f64(i8* %0, i32 8) @@ -441,7 +441,7 @@ entry: define %struct.int8x16x3_t @test_vld3q_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld3q_dup_s8 -; CHECK: ld3r {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, [x0] entry: %vld_dup = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1) %0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld_dup, 0 @@ -458,7 +458,7 @@ entry: define %struct.int16x8x3_t @test_vld3q_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld3q_dup_s16 -; CHECK: ld3r {{{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h }, [x0] entry: %0 = bitcast i16* %a to i8* %vld_dup = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* %0, <8 x i16> undef, <8 x i16> undef, <8 x i16> undef, i32 0, i32 2) @@ -476,7 +476,7 @@ entry: define %struct.int32x4x3_t @test_vld3q_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld3q_dup_s32 -; CHECK: ld3r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0] entry: %0 = bitcast i32* %a to i8* %vld_dup = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3lane.v4i32(i8* %0, <4 x i32> undef, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4) @@ -494,7 +494,7 @@ entry: define %struct.int64x2x3_t @test_vld3q_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld3q_dup_s64 -; CHECK: ld3r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0] entry: %0 = bitcast i64* %a to i8* %vld_dup = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld3lane.v2i64(i8* %0, <2 x i64> undef, <2 x i64> undef, <2 x i64> undef, i32 0, i32 8) @@ -512,7 +512,7 @@ entry: define %struct.float32x4x3_t @test_vld3q_dup_f32(float* %a) { ; CHECK-LABEL: test_vld3q_dup_f32 -; CHECK: ld3r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0] entry: %0 = bitcast float* %a to i8* %vld_dup = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3lane.v4f32(i8* %0, <4 x float> undef, <4 x float> undef, <4 x float> undef, i32 0, i32 4) @@ -530,7 +530,7 @@ entry: define %struct.float64x2x3_t @test_vld3q_dup_f64(double* %a) { ; CHECK-LABEL: test_vld3q_dup_f64 -; CHECK: ld3r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0] entry: %0 = bitcast double* %a to i8* %vld_dup = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld3lane.v2f64(i8* %0, <2 x double> undef, <2 x double> undef, <2 x double> undef, i32 0, i32 8) @@ -548,7 +548,7 @@ entry: define %struct.int8x8x3_t @test_vld3_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld3_dup_s8 -; CHECK: ld3r {{{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b }, [x0] entry: %vld_dup = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) %0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld_dup, 0 @@ -565,7 +565,7 @@ entry: define %struct.int16x4x3_t @test_vld3_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld3_dup_s16 -; CHECK: ld3r {{{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h }, [x0] entry: %0 = bitcast i16* %a to i8* %vld_dup = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16(i8* %0, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) @@ -583,7 +583,7 @@ entry: define %struct.int32x2x3_t @test_vld3_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld3_dup_s32 -; CHECK: ld3r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0] entry: %0 = bitcast i32* %a to i8* %vld_dup = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3lane.v2i32(i8* %0, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4) @@ -601,7 +601,7 @@ entry: define %struct.int64x1x3_t @test_vld3_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld3_dup_s64 -; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0] +; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0] entry: %0 = bitcast i64* %a to i8* %vld_dup = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld3.v1i64(i8* %0, i32 8) @@ -616,7 +616,7 @@ entry: define %struct.float32x2x3_t @test_vld3_dup_f32(float* %a) { ; CHECK-LABEL: test_vld3_dup_f32 -; CHECK: ld3r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0] +; CHECK: ld3r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0] entry: %0 = bitcast float* %a to i8* %vld_dup = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld3lane.v2f32(i8* %0, <2 x float> undef, <2 x float> undef, <2 x float> undef, i32 0, i32 4) @@ -634,7 +634,7 @@ entry: define %struct.float64x1x3_t @test_vld3_dup_f64(double* %a) { ; CHECK-LABEL: test_vld3_dup_f64 -; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0] +; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0] entry: %0 = bitcast double* %a to i8* %vld_dup = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neon.vld3.v1f64(i8* %0, i32 8) @@ -649,7 +649,7 @@ entry: define %struct.int8x16x4_t @test_vld4q_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld4q_dup_s8 -; CHECK: ld4r {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, [x0] entry: %vld_dup = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1) %0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld_dup, 0 @@ -669,7 +669,7 @@ entry: define %struct.int16x8x4_t @test_vld4q_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld4q_dup_s16 -; CHECK: ld4r {{{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h }, [x0] entry: %0 = bitcast i16* %a to i8* %vld_dup = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4lane.v8i16(i8* %0, <8 x i16> undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> undef, i32 0, i32 2) @@ -690,7 +690,7 @@ entry: define %struct.int32x4x4_t @test_vld4q_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld4q_dup_s32 -; CHECK: ld4r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0] entry: %0 = bitcast i32* %a to i8* %vld_dup = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld4lane.v4i32(i8* %0, <4 x i32> undef, <4 x i32> undef, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4) @@ -711,7 +711,7 @@ entry: define %struct.int64x2x4_t @test_vld4q_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld4q_dup_s64 -; CHECK: ld4r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0] entry: %0 = bitcast i64* %a to i8* %vld_dup = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld4lane.v2i64(i8* %0, <2 x i64> undef, <2 x i64> undef, <2 x i64> undef, <2 x i64> undef, i32 0, i32 8) @@ -732,7 +732,7 @@ entry: define %struct.float32x4x4_t @test_vld4q_dup_f32(float* %a) { ; CHECK-LABEL: test_vld4q_dup_f32 -; CHECK: ld4r {{{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s }, [x0] entry: %0 = bitcast float* %a to i8* %vld_dup = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld4lane.v4f32(i8* %0, <4 x float> undef, <4 x float> undef, <4 x float> undef, <4 x float> undef, i32 0, i32 4) @@ -753,7 +753,7 @@ entry: define %struct.float64x2x4_t @test_vld4q_dup_f64(double* %a) { ; CHECK-LABEL: test_vld4q_dup_f64 -; CHECK: ld4r {{{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d }, [x0] entry: %0 = bitcast double* %a to i8* %vld_dup = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld4lane.v2f64(i8* %0, <2 x double> undef, <2 x double> undef, <2 x double> undef, <2 x double> undef, i32 0, i32 8) @@ -774,7 +774,7 @@ entry: define %struct.int8x8x4_t @test_vld4_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld4_dup_s8 -; CHECK: ld4r {{{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b }, [x0] entry: %vld_dup = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) %0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld_dup, 0 @@ -794,7 +794,7 @@ entry: define %struct.int16x4x4_t @test_vld4_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld4_dup_s16 -; CHECK: ld4r {{{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h }, [x0] entry: %0 = bitcast i16* %a to i8* %vld_dup = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4lane.v4i16(i8* %0, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) @@ -815,7 +815,7 @@ entry: define %struct.int32x2x4_t @test_vld4_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld4_dup_s32 -; CHECK: ld4r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0] entry: %0 = bitcast i32* %a to i8* %vld_dup = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4lane.v2i32(i8* %0, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4) @@ -836,7 +836,7 @@ entry: define %struct.int64x1x4_t @test_vld4_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld4_dup_s64 -; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0] +; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0] entry: %0 = bitcast i64* %a to i8* %vld_dup = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld4.v1i64(i8* %0, i32 8) @@ -853,7 +853,7 @@ entry: define %struct.float32x2x4_t @test_vld4_dup_f32(float* %a) { ; CHECK-LABEL: test_vld4_dup_f32 -; CHECK: ld4r {{{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s}, [x0] +; CHECK: ld4r { {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s }, [x0] entry: %0 = bitcast float* %a to i8* %vld_dup = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld4lane.v2f32(i8* %0, <2 x float> undef, <2 x float> undef, <2 x float> undef, <2 x float> undef, i32 0, i32 4) @@ -874,7 +874,7 @@ entry: define %struct.float64x1x4_t @test_vld4_dup_f64(double* %a) { ; CHECK-LABEL: test_vld4_dup_f64 -; CHECK: ld1 {{{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d}, [x0] +; CHECK: ld1 { {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d }, [x0] entry: %0 = bitcast double* %a to i8* %vld_dup = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm.neon.vld4.v1f64(i8* %0, i32 8) @@ -891,7 +891,7 @@ entry: define <16 x i8> @test_vld1q_lane_s8(i8* %a, <16 x i8> %b) { ; CHECK-LABEL: test_vld1q_lane_s8 -; CHECK: ld1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %0 = load i8* %a, align 1 %vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15 @@ -900,7 +900,7 @@ entry: define <8 x i16> @test_vld1q_lane_s16(i16* %a, <8 x i16> %b) { ; CHECK-LABEL: test_vld1q_lane_s16 -; CHECK: ld1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %0 = load i16* %a, align 2 %vld1_lane = insertelement <8 x i16> %b, i16 %0, i32 7 @@ -909,7 +909,7 @@ entry: define <4 x i32> @test_vld1q_lane_s32(i32* %a, <4 x i32> %b) { ; CHECK-LABEL: test_vld1q_lane_s32 -; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = load i32* %a, align 4 %vld1_lane = insertelement <4 x i32> %b, i32 %0, i32 3 @@ -918,7 +918,7 @@ entry: define <2 x i64> @test_vld1q_lane_s64(i64* %a, <2 x i64> %b) { ; CHECK-LABEL: test_vld1q_lane_s64 -; CHECK: ld1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %0 = load i64* %a, align 8 %vld1_lane = insertelement <2 x i64> %b, i64 %0, i32 1 @@ -927,7 +927,7 @@ entry: define <4 x float> @test_vld1q_lane_f32(float* %a, <4 x float> %b) { ; CHECK-LABEL: test_vld1q_lane_f32 -; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = load float* %a, align 4 %vld1_lane = insertelement <4 x float> %b, float %0, i32 3 @@ -936,7 +936,7 @@ entry: define <2 x double> @test_vld1q_lane_f64(double* %a, <2 x double> %b) { ; CHECK-LABEL: test_vld1q_lane_f64 -; CHECK: ld1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %0 = load double* %a, align 8 %vld1_lane = insertelement <2 x double> %b, double %0, i32 1 @@ -945,7 +945,7 @@ entry: define <8 x i8> @test_vld1_lane_s8(i8* %a, <8 x i8> %b) { ; CHECK-LABEL: test_vld1_lane_s8 -; CHECK: ld1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %0 = load i8* %a, align 1 %vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7 @@ -954,7 +954,7 @@ entry: define <4 x i16> @test_vld1_lane_s16(i16* %a, <4 x i16> %b) { ; CHECK-LABEL: test_vld1_lane_s16 -; CHECK: ld1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %0 = load i16* %a, align 2 %vld1_lane = insertelement <4 x i16> %b, i16 %0, i32 3 @@ -963,7 +963,7 @@ entry: define <2 x i32> @test_vld1_lane_s32(i32* %a, <2 x i32> %b) { ; CHECK-LABEL: test_vld1_lane_s32 -; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = load i32* %a, align 4 %vld1_lane = insertelement <2 x i32> %b, i32 %0, i32 1 @@ -972,7 +972,7 @@ entry: define <1 x i64> @test_vld1_lane_s64(i64* %a, <1 x i64> %b) { ; CHECK-LABEL: test_vld1_lane_s64 -; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0] entry: %0 = load i64* %a, align 8 %vld1_lane = insertelement <1 x i64> undef, i64 %0, i32 0 @@ -981,7 +981,7 @@ entry: define <2 x float> @test_vld1_lane_f32(float* %a, <2 x float> %b) { ; CHECK-LABEL: test_vld1_lane_f32 -; CHECK: ld1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = load float* %a, align 4 %vld1_lane = insertelement <2 x float> %b, float %0, i32 1 @@ -990,7 +990,7 @@ entry: define <1 x double> @test_vld1_lane_f64(double* %a, <1 x double> %b) { ; CHECK-LABEL: test_vld1_lane_f64 -; CHECK: ld1r {{{v[0-9]+}}.1d}, [x0] +; CHECK: ld1r { {{v[0-9]+}}.1d }, [x0] entry: %0 = load double* %a, align 8 %vld1_lane = insertelement <1 x double> undef, double %0, i32 0 @@ -999,7 +999,7 @@ entry: define %struct.int16x8x2_t @test_vld2q_lane_s16(i16* %a, [2 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vld2q_lane_s16 -; CHECK: ld2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <8 x i16>] %b.coerce, 1 @@ -1014,7 +1014,7 @@ entry: define %struct.int32x4x2_t @test_vld2q_lane_s32(i32* %a, [2 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vld2q_lane_s32 -; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %b.coerce, 1 @@ -1029,7 +1029,7 @@ entry: define %struct.int64x2x2_t @test_vld2q_lane_s64(i64* %a, [2 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vld2q_lane_s64 -; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x i64>] %b.coerce, 1 @@ -1044,7 +1044,7 @@ entry: define %struct.float32x4x2_t @test_vld2q_lane_f32(float* %a, [2 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vld2q_lane_f32 -; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x float>] %b.coerce, 1 @@ -1059,7 +1059,7 @@ entry: define %struct.float64x2x2_t @test_vld2q_lane_f64(double* %a, [2 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vld2q_lane_f64 -; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x double>] %b.coerce, 1 @@ -1074,7 +1074,7 @@ entry: define %struct.int8x8x2_t @test_vld2_lane_s8(i8* %a, [2 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vld2_lane_s8 -; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <8 x i8>] %b.coerce, 1 @@ -1088,7 +1088,7 @@ entry: define %struct.int16x4x2_t @test_vld2_lane_s16(i16* %a, [2 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vld2_lane_s16 -; CHECK: ld2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x i16>] %b.coerce, 1 @@ -1103,7 +1103,7 @@ entry: define %struct.int32x2x2_t @test_vld2_lane_s32(i32* %a, [2 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vld2_lane_s32 -; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %b.coerce, 1 @@ -1118,7 +1118,7 @@ entry: define %struct.int64x1x2_t @test_vld2_lane_s64(i64* %a, [2 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vld2_lane_s64 -; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <1 x i64>] %b.coerce, 1 @@ -1133,7 +1133,7 @@ entry: define %struct.float32x2x2_t @test_vld2_lane_f32(float* %a, [2 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vld2_lane_f32 -; CHECK: ld2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x float>] %b.coerce, 1 @@ -1148,7 +1148,7 @@ entry: define %struct.float64x1x2_t @test_vld2_lane_f64(double* %a, [2 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vld2_lane_f64 -; CHECK: ld2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <1 x double>] %b.coerce, 1 @@ -1163,7 +1163,7 @@ entry: define %struct.int16x8x3_t @test_vld3q_lane_s16(i16* %a, [3 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vld3q_lane_s16 -; CHECK: ld3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <8 x i16>] %b.coerce, 1 @@ -1181,7 +1181,7 @@ entry: define %struct.int32x4x3_t @test_vld3q_lane_s32(i32* %a, [3 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vld3q_lane_s32 -; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x i32>] %b.coerce, 1 @@ -1199,7 +1199,7 @@ entry: define %struct.int64x2x3_t @test_vld3q_lane_s64(i64* %a, [3 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vld3q_lane_s64 -; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x i64>] %b.coerce, 1 @@ -1217,7 +1217,7 @@ entry: define %struct.float32x4x3_t @test_vld3q_lane_f32(float* %a, [3 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vld3q_lane_f32 -; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x float>] %b.coerce, 1 @@ -1235,7 +1235,7 @@ entry: define %struct.float64x2x3_t @test_vld3q_lane_f64(double* %a, [3 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vld3q_lane_f64 -; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x double>] %b.coerce, 1 @@ -1253,7 +1253,7 @@ entry: define %struct.int8x8x3_t @test_vld3_lane_s8(i8* %a, [3 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vld3_lane_s8 -; CHECK: ld3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <8 x i8>] %b.coerce, 1 @@ -1270,7 +1270,7 @@ entry: define %struct.int16x4x3_t @test_vld3_lane_s16(i16* %a, [3 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vld3_lane_s16 -; CHECK: ld3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x i16>] %b.coerce, 1 @@ -1288,7 +1288,7 @@ entry: define %struct.int32x2x3_t @test_vld3_lane_s32(i32* %a, [3 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vld3_lane_s32 -; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x i32>] %b.coerce, 1 @@ -1306,7 +1306,7 @@ entry: define %struct.int64x1x3_t @test_vld3_lane_s64(i64* %a, [3 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vld3_lane_s64 -; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <1 x i64>] %b.coerce, 1 @@ -1324,7 +1324,7 @@ entry: define %struct.float32x2x3_t @test_vld3_lane_f32(float* %a, [3 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vld3_lane_f32 -; CHECK: ld3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x float>] %b.coerce, 1 @@ -1342,7 +1342,7 @@ entry: define %struct.float64x1x3_t @test_vld3_lane_f64(double* %a, [3 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vld3_lane_f64 -; CHECK: ld3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <1 x double>] %b.coerce, 1 @@ -1360,7 +1360,7 @@ entry: define %struct.int8x16x4_t @test_vld4q_lane_s8(i8* %a, [4 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vld4q_lane_s8 -; CHECK: ld4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -1380,7 +1380,7 @@ entry: define %struct.int16x8x4_t @test_vld4q_lane_s16(i16* %a, [4 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vld4q_lane_s16 -; CHECK: ld4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <8 x i16>] %b.coerce, 1 @@ -1401,7 +1401,7 @@ entry: define %struct.int32x4x4_t @test_vld4q_lane_s32(i32* %a, [4 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vld4q_lane_s32 -; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x i32>] %b.coerce, 1 @@ -1422,7 +1422,7 @@ entry: define %struct.int64x2x4_t @test_vld4q_lane_s64(i64* %a, [4 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vld4q_lane_s64 -; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x i64>] %b.coerce, 1 @@ -1443,7 +1443,7 @@ entry: define %struct.float32x4x4_t @test_vld4q_lane_f32(float* %a, [4 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vld4q_lane_f32 -; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x float>] %b.coerce, 1 @@ -1464,7 +1464,7 @@ entry: define %struct.float64x2x4_t @test_vld4q_lane_f64(double* %a, [4 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vld4q_lane_f64 -; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x double>] %b.coerce, 1 @@ -1485,7 +1485,7 @@ entry: define %struct.int8x8x4_t @test_vld4_lane_s8(i8* %a, [4 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vld4_lane_s8 -; CHECK: ld4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <8 x i8>] %b.coerce, 1 @@ -1505,7 +1505,7 @@ entry: define %struct.int16x4x4_t @test_vld4_lane_s16(i16* %a, [4 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vld4_lane_s16 -; CHECK: ld4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x i16>] %b.coerce, 1 @@ -1526,7 +1526,7 @@ entry: define %struct.int32x2x4_t @test_vld4_lane_s32(i32* %a, [4 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vld4_lane_s32 -; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x i32>] %b.coerce, 1 @@ -1547,7 +1547,7 @@ entry: define %struct.int64x1x4_t @test_vld4_lane_s64(i64* %a, [4 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vld4_lane_s64 -; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <1 x i64>] %b.coerce, 1 @@ -1568,7 +1568,7 @@ entry: define %struct.float32x2x4_t @test_vld4_lane_f32(float* %a, [4 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vld4_lane_f32 -; CHECK: ld4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x float>] %b.coerce, 1 @@ -1589,7 +1589,7 @@ entry: define %struct.float64x1x4_t @test_vld4_lane_f64(double* %a, [4 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vld4_lane_f64 -; CHECK: ld4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: ld4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <1 x double>] %b.coerce, 1 @@ -1610,7 +1610,7 @@ entry: define void @test_vst1q_lane_s8(i8* %a, <16 x i8> %b) { ; CHECK-LABEL: test_vst1q_lane_s8 -; CHECK: st1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %0 = extractelement <16 x i8> %b, i32 15 store i8 %0, i8* %a, align 1 @@ -1619,7 +1619,7 @@ entry: define void @test_vst1q_lane_s16(i16* %a, <8 x i16> %b) { ; CHECK-LABEL: test_vst1q_lane_s16 -; CHECK: st1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %0 = extractelement <8 x i16> %b, i32 7 store i16 %0, i16* %a, align 2 @@ -1628,7 +1628,7 @@ entry: define void @test_vst1q_lane_s32(i32* %a, <4 x i32> %b) { ; CHECK-LABEL: test_vst1q_lane_s32 -; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = extractelement <4 x i32> %b, i32 3 store i32 %0, i32* %a, align 4 @@ -1637,7 +1637,7 @@ entry: define void @test_vst1q_lane_s64(i64* %a, <2 x i64> %b) { ; CHECK-LABEL: test_vst1q_lane_s64 -; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %0 = extractelement <2 x i64> %b, i32 1 store i64 %0, i64* %a, align 8 @@ -1646,7 +1646,7 @@ entry: define void @test_vst1q_lane_f32(float* %a, <4 x float> %b) { ; CHECK-LABEL: test_vst1q_lane_f32 -; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = extractelement <4 x float> %b, i32 3 store float %0, float* %a, align 4 @@ -1655,7 +1655,7 @@ entry: define void @test_vst1q_lane_f64(double* %a, <2 x double> %b) { ; CHECK-LABEL: test_vst1q_lane_f64 -; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %0 = extractelement <2 x double> %b, i32 1 store double %0, double* %a, align 8 @@ -1664,7 +1664,7 @@ entry: define void @test_vst1_lane_s8(i8* %a, <8 x i8> %b) { ; CHECK-LABEL: test_vst1_lane_s8 -; CHECK: st1 {{{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %0 = extractelement <8 x i8> %b, i32 7 store i8 %0, i8* %a, align 1 @@ -1673,7 +1673,7 @@ entry: define void @test_vst1_lane_s16(i16* %a, <4 x i16> %b) { ; CHECK-LABEL: test_vst1_lane_s16 -; CHECK: st1 {{{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %0 = extractelement <4 x i16> %b, i32 3 store i16 %0, i16* %a, align 2 @@ -1682,7 +1682,7 @@ entry: define void @test_vst1_lane_s32(i32* %a, <2 x i32> %b) { ; CHECK-LABEL: test_vst1_lane_s32 -; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = extractelement <2 x i32> %b, i32 1 store i32 %0, i32* %a, align 4 @@ -1691,7 +1691,7 @@ entry: define void @test_vst1_lane_s64(i64* %a, <1 x i64> %b) { ; CHECK-LABEL: test_vst1_lane_s64 -; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %0 = extractelement <1 x i64> %b, i32 0 store i64 %0, i64* %a, align 8 @@ -1700,7 +1700,7 @@ entry: define void @test_vst1_lane_f32(float* %a, <2 x float> %b) { ; CHECK-LABEL: test_vst1_lane_f32 -; CHECK: st1 {{{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %0 = extractelement <2 x float> %b, i32 1 store float %0, float* %a, align 4 @@ -1709,7 +1709,7 @@ entry: define void @test_vst1_lane_f64(double* %a, <1 x double> %b) { ; CHECK-LABEL: test_vst1_lane_f64 -; CHECK: st1 {{{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %0 = extractelement <1 x double> %b, i32 0 store double %0, double* %a, align 8 @@ -1718,7 +1718,7 @@ entry: define void @test_vst2q_lane_s8(i8* %a, [2 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst2q_lane_s8 -; CHECK: st2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -1728,7 +1728,7 @@ entry: define void @test_vst2q_lane_s16(i16* %a, [2 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst2q_lane_s16 -; CHECK: st2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <8 x i16>] %b.coerce, 1 @@ -1739,7 +1739,7 @@ entry: define void @test_vst2q_lane_s32(i32* %a, [2 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst2q_lane_s32 -; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %b.coerce, 1 @@ -1750,7 +1750,7 @@ entry: define void @test_vst2q_lane_s64(i64* %a, [2 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst2q_lane_s64 -; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x i64>] %b.coerce, 1 @@ -1761,7 +1761,7 @@ entry: define void @test_vst2q_lane_f32(float* %a, [2 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vst2q_lane_f32 -; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x float>] %b.coerce, 1 @@ -1772,7 +1772,7 @@ entry: define void @test_vst2q_lane_f64(double* %a, [2 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vst2q_lane_f64 -; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x double>] %b.coerce, 1 @@ -1783,7 +1783,7 @@ entry: define void @test_vst2_lane_s8(i8* %a, [2 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst2_lane_s8 -; CHECK: st2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <8 x i8>] %b.coerce, 1 @@ -1793,7 +1793,7 @@ entry: define void @test_vst2_lane_s16(i16* %a, [2 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst2_lane_s16 -; CHECK: st2 {{{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <4 x i16>] %b.coerce, 1 @@ -1804,7 +1804,7 @@ entry: define void @test_vst2_lane_s32(i32* %a, [2 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst2_lane_s32 -; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %b.coerce, 1 @@ -1815,7 +1815,7 @@ entry: define void @test_vst2_lane_s64(i64* %a, [2 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst2_lane_s64 -; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <1 x i64>] %b.coerce, 1 @@ -1826,7 +1826,7 @@ entry: define void @test_vst2_lane_f32(float* %a, [2 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vst2_lane_f32 -; CHECK: st2 {{{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <2 x float>] %b.coerce, 1 @@ -1837,7 +1837,7 @@ entry: define void @test_vst2_lane_f64(double* %a, [2 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vst2_lane_f64 -; CHECK: st2 {{{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st2 { {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [2 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [2 x <1 x double>] %b.coerce, 1 @@ -1848,7 +1848,7 @@ entry: define void @test_vst3q_lane_s8(i8* %a, [3 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst3q_lane_s8 -; CHECK: st3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -1859,7 +1859,7 @@ entry: define void @test_vst3q_lane_s16(i16* %a, [3 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst3q_lane_s16 -; CHECK: st3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <8 x i16>] %b.coerce, 1 @@ -1871,7 +1871,7 @@ entry: define void @test_vst3q_lane_s32(i32* %a, [3 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst3q_lane_s32 -; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x i32>] %b.coerce, 1 @@ -1883,7 +1883,7 @@ entry: define void @test_vst3q_lane_s64(i64* %a, [3 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst3q_lane_s64 -; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x i64>] %b.coerce, 1 @@ -1895,7 +1895,7 @@ entry: define void @test_vst3q_lane_f32(float* %a, [3 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vst3q_lane_f32 -; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x float>] %b.coerce, 1 @@ -1907,7 +1907,7 @@ entry: define void @test_vst3q_lane_f64(double* %a, [3 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vst3q_lane_f64 -; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x double>] %b.coerce, 1 @@ -1919,7 +1919,7 @@ entry: define void @test_vst3_lane_s8(i8* %a, [3 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst3_lane_s8 -; CHECK: st3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <8 x i8>] %b.coerce, 1 @@ -1930,7 +1930,7 @@ entry: define void @test_vst3_lane_s16(i16* %a, [3 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst3_lane_s16 -; CHECK: st3 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <4 x i16>] %b.coerce, 1 @@ -1942,7 +1942,7 @@ entry: define void @test_vst3_lane_s32(i32* %a, [3 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst3_lane_s32 -; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x i32>] %b.coerce, 1 @@ -1954,7 +1954,7 @@ entry: define void @test_vst3_lane_s64(i64* %a, [3 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst3_lane_s64 -; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <1 x i64>] %b.coerce, 1 @@ -1966,7 +1966,7 @@ entry: define void @test_vst3_lane_f32(float* %a, [3 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vst3_lane_f32 -; CHECK: st3 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <2 x float>] %b.coerce, 1 @@ -1978,7 +1978,7 @@ entry: define void @test_vst3_lane_f64(double* %a, [3 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vst3_lane_f64 -; CHECK: st3 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st3 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [3 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [3 x <1 x double>] %b.coerce, 1 @@ -1990,7 +1990,7 @@ entry: define void @test_vst4q_lane_s8(i16* %a, [4 x <16 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst4q_lane_s8 -; CHECK: st4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <16 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -2003,7 +2003,7 @@ entry: define void @test_vst4q_lane_s16(i16* %a, [4 x <8 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst4q_lane_s16 -; CHECK: st4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <8 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <8 x i16>] %b.coerce, 1 @@ -2016,7 +2016,7 @@ entry: define void @test_vst4q_lane_s32(i32* %a, [4 x <4 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst4q_lane_s32 -; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <4 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x i32>] %b.coerce, 1 @@ -2029,7 +2029,7 @@ entry: define void @test_vst4q_lane_s64(i64* %a, [4 x <2 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst4q_lane_s64 -; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x i64>] %b.coerce, 1 @@ -2042,7 +2042,7 @@ entry: define void @test_vst4q_lane_f32(float* %a, [4 x <4 x float>] %b.coerce) { ; CHECK-LABEL: test_vst4q_lane_f32 -; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <4 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x float>] %b.coerce, 1 @@ -2055,7 +2055,7 @@ entry: define void @test_vst4q_lane_f64(double* %a, [4 x <2 x double>] %b.coerce) { ; CHECK-LABEL: test_vst4q_lane_f64 -; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x double>] %b.coerce, 1 @@ -2068,7 +2068,7 @@ entry: define void @test_vst4_lane_s8(i8* %a, [4 x <8 x i8>] %b.coerce) { ; CHECK-LABEL: test_vst4_lane_s8 -; CHECK: st4 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <8 x i8>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <8 x i8>] %b.coerce, 1 @@ -2080,7 +2080,7 @@ entry: define void @test_vst4_lane_s16(i16* %a, [4 x <4 x i16>] %b.coerce) { ; CHECK-LABEL: test_vst4_lane_s16 -; CHECK: st4 {{{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h, {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <4 x i16>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <4 x i16>] %b.coerce, 1 @@ -2093,7 +2093,7 @@ entry: define void @test_vst4_lane_s32(i32* %a, [4 x <2 x i32>] %b.coerce) { ; CHECK-LABEL: test_vst4_lane_s32 -; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x i32>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x i32>] %b.coerce, 1 @@ -2106,7 +2106,7 @@ entry: define void @test_vst4_lane_s64(i64* %a, [4 x <1 x i64>] %b.coerce) { ; CHECK-LABEL: test_vst4_lane_s64 -; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <1 x i64>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <1 x i64>] %b.coerce, 1 @@ -2119,7 +2119,7 @@ entry: define void @test_vst4_lane_f32(float* %a, [4 x <2 x float>] %b.coerce) { ; CHECK-LABEL: test_vst4_lane_f32 -; CHECK: st4 {{{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s, {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <2 x float>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <2 x float>] %b.coerce, 1 @@ -2132,7 +2132,7 @@ entry: define void @test_vst4_lane_f64(double* %a, [4 x <1 x double>] %b.coerce) { ; CHECK-LABEL: test_vst4_lane_f64 -; CHECK: st4 {{{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d}[{{[0-9]+}}], [x0] +; CHECK: st4 { {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d, {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: %b.coerce.fca.0.extract = extractvalue [4 x <1 x double>] %b.coerce, 0 %b.coerce.fca.1.extract = extractvalue [4 x <1 x double>] %b.coerce, 1 @@ -2224,7 +2224,7 @@ declare void @llvm.arm.neon.vst4lane.v1f64(i8*, <1 x double>, <1 x double>, <1 x define %struct.int8x16x2_t @test_vld2q_lane_s8(i8* readonly %ptr, [2 x <16 x i8>] %src.coerce) { ; CHECK-LABEL: test_vld2q_lane_s8 -; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0] +; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0] entry: %src.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %src.coerce, 0 %src.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %src.coerce, 1 @@ -2238,7 +2238,7 @@ entry: define %struct.uint8x16x2_t @test_vld2q_lane_u8(i8* readonly %ptr, [2 x <16 x i8>] %src.coerce) { ; CHECK-LABEL: test_vld2q_lane_u8 -; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0] +; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0] entry: %src.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %src.coerce, 0 %src.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %src.coerce, 1 @@ -2252,7 +2252,7 @@ entry: define %struct.poly8x16x2_t @test_vld2q_lane_p8(i8* readonly %ptr, [2 x <16 x i8>] %src.coerce) { ; CHECK-LABEL: test_vld2q_lane_p8 -; CHECK: ld2 {{{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0] +; CHECK: ld2 { {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0] entry: %src.coerce.fca.0.extract = extractvalue [2 x <16 x i8>] %src.coerce, 0 %src.coerce.fca.1.extract = extractvalue [2 x <16 x i8>] %src.coerce, 1 @@ -2266,7 +2266,7 @@ entry: define %struct.int8x16x3_t @test_vld3q_lane_s8(i8* readonly %ptr, [3 x <16 x i8>] %src.coerce) { ; CHECK-LABEL: test_vld3q_lane_s8 -; CHECK: ld3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0] +; CHECK: ld3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0] entry: %src.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %src.coerce, 0 %src.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %src.coerce, 1 @@ -2283,7 +2283,7 @@ entry: define %struct.uint8x16x3_t @test_vld3q_lane_u8(i8* readonly %ptr, [3 x <16 x i8>] %src.coerce) { ; CHECK-LABEL: test_vld3q_lane_u8 -; CHECK: ld3 {{{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b}[15], [x0] +; CHECK: ld3 { {{v[0-9]+}}.b, {{v[0-9]+}}.b, {{v[0-9]+}}.b }[15], [x0] entry: %src.coerce.fca.0.extract = extractvalue [3 x <16 x i8>] %src.coerce, 0 %src.coerce.fca.1.extract = extractvalue [3 x <16 x i8>] %src.coerce, 1 diff --git a/test/CodeGen/AArch64/neon-simd-ldst.ll b/test/CodeGen/AArch64/neon-simd-ldst.ll index cb0a2d237c..7c78b69334 100644 --- a/test/CodeGen/AArch64/neon-simd-ldst.ll +++ b/test/CodeGen/AArch64/neon-simd-ldst.ll @@ -3,8 +3,8 @@ define void @test_ldstq_4v(i8* noalias %io, i32 %count) { ; CHECK-LABEL: test_ldstq_4v -; CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] -; CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] +; CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] +; CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] entry: %tobool62 = icmp eq i32 %count, 0 br i1 %tobool62, label %while.end, label %while.body @@ -31,8 +31,8 @@ declare void @llvm.arm.neon.vst4.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 define void @test_ldstq_3v(i8* noalias %io, i32 %count) { ; CHECK-LABEL: test_ldstq_3v -; CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] -; CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] +; CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] +; CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] entry: %tobool47 = icmp eq i32 %count, 0 br i1 %tobool47, label %while.end, label %while.body @@ -58,8 +58,8 @@ declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32 define void @test_ldstq_2v(i8* noalias %io, i32 %count) { ; CHECK-LABEL: test_ldstq_2v -; CHECK: ld2 {v0.16b, v1.16b}, [x0] -; CHECK: st2 {v0.16b, v1.16b}, [x0] +; CHECK: ld2 { v0.16b, v1.16b }, [x0] +; CHECK: st2 { v0.16b, v1.16b }, [x0] entry: %tobool22 = icmp eq i32 %count, 0 br i1 %tobool22, label %while.end, label %while.body @@ -84,8 +84,8 @@ declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>, i32) define void @test_ldst_4v(i8* noalias %io, i32 %count) { ; CHECK-LABEL: test_ldst_4v -; CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] -; CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +; CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] +; CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] entry: %tobool42 = icmp eq i32 %count, 0 br i1 %tobool42, label %while.end, label %while.body @@ -112,8 +112,8 @@ declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8 define void @test_ldst_3v(i8* noalias %io, i32 %count) { ; CHECK-LABEL: test_ldst_3v -; CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] -; CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] +; CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] +; CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] entry: %tobool32 = icmp eq i32 %count, 0 br i1 %tobool32, label %while.end, label %while.body @@ -139,8 +139,8 @@ declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) define void @test_ldst_2v(i8* noalias %io, i32 %count) { ; CHECK-LABEL: test_ldst_2v -; CHECK: ld2 {v0.8b, v1.8b}, [x0] -; CHECK: st2 {v0.8b, v1.8b}, [x0] +; CHECK: ld2 { v0.8b, v1.8b }, [x0] +; CHECK: st2 { v0.8b, v1.8b }, [x0] entry: %tobool22 = icmp eq i32 %count, 0 br i1 %tobool22, label %while.end, label %while.body diff --git a/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll b/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll index 156fe1db0f..8acf6b792e 100644 --- a/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll +++ b/test/CodeGen/AArch64/neon-simd-post-ldst-multi-elem.ll @@ -3,7 +3,7 @@ ;Check for a post-increment updating load. define <4 x i16> @test_vld1_fx_update(i16** %ptr) nounwind { ; CHECK: test_vld1_fx_update -; CHECK: ld1 {v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], #8 +; CHECK: ld1 { v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}], #8 %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 2) @@ -15,7 +15,7 @@ define <4 x i16> @test_vld1_fx_update(i16** %ptr) nounwind { ;Check for a post-increment updating load with register increment. define <2 x i32> @test_vld1_reg_update(i32** %ptr, i32 %inc) nounwind { ; CHECK: test_vld1_reg_update -; CHECK: ld1 {v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld1 { v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 4) @@ -26,7 +26,7 @@ define <2 x i32> @test_vld1_reg_update(i32** %ptr, i32 %inc) nounwind { define <2 x float> @test_vld2_fx_update(float** %ptr) nounwind { ; CHECK: test_vld2_fx_update -; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #16 +; CHECK: ld2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], #16 %A = load float** %ptr %tmp0 = bitcast float* %A to i8* %tmp1 = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 4) @@ -38,7 +38,7 @@ define <2 x float> @test_vld2_fx_update(float** %ptr) nounwind { define <16 x i8> @test_vld2_reg_update(i8** %ptr, i32 %inc) nounwind { ; CHECK: test_vld2_reg_update -; CHECK: ld2 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld2 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %A = load i8** %ptr %tmp0 = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8* %A, i32 1) %tmp1 = extractvalue { <16 x i8>, <16 x i8> } %tmp0, 0 @@ -49,7 +49,7 @@ define <16 x i8> @test_vld2_reg_update(i8** %ptr, i32 %inc) nounwind { define <4 x i32> @test_vld3_fx_update(i32** %ptr) nounwind { ; CHECK: test_vld3_fx_update -; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #48 +; CHECK: ld3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], #48 %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 4) @@ -61,7 +61,7 @@ define <4 x i32> @test_vld3_fx_update(i32** %ptr) nounwind { define <4 x i16> @test_vld3_reg_update(i16** %ptr, i32 %inc) nounwind { ; CHECK: test_vld3_reg_update -; CHECK: ld3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld3 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 2) @@ -73,7 +73,7 @@ define <4 x i16> @test_vld3_reg_update(i16** %ptr, i32 %inc) nounwind { define <8 x i16> @test_vld4_fx_update(i16** %ptr) nounwind { ; CHECK: test_vld4_fx_update -; CHECK: ld4 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], #64 +; CHECK: ld4 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], #64 %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) @@ -85,7 +85,7 @@ define <8 x i16> @test_vld4_fx_update(i16** %ptr) nounwind { define <8 x i8> @test_vld4_reg_update(i8** %ptr, i32 %inc) nounwind { ; CHECK: test_vld4_reg_update -; CHECK: ld4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld4 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %A = load i8** %ptr %tmp0 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8* %A, i32 1) %tmp1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %tmp0, 0 @@ -96,7 +96,7 @@ define <8 x i8> @test_vld4_reg_update(i8** %ptr, i32 %inc) nounwind { define void @test_vst1_fx_update(float** %ptr, <2 x float> %B) nounwind { ; CHECK: test_vst1_fx_update -; CHECK: st1 {v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}], #8 +; CHECK: st1 { v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}], #8 %A = load float** %ptr %tmp0 = bitcast float* %A to i8* call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %B, i32 4) @@ -107,7 +107,7 @@ define void @test_vst1_fx_update(float** %ptr, <2 x float> %B) nounwind { define void @test_vst1_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind { ; CHECK: test_vst1_reg_update -; CHECK: st1 {v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st1 { v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}], x{{[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %B, i32 2) @@ -118,7 +118,7 @@ define void @test_vst1_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind { define void @test_vst2_fx_update(i64** %ptr, <1 x i64> %B) nounwind { ; CHECK: test_vst2_fx_update -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [{{x[0-9]+|sp}}], #16 +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [{{x[0-9]+|sp}}], #16 %A = load i64** %ptr %tmp0 = bitcast i64* %A to i8* call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %B, <1 x i64> %B, i32 8) @@ -129,7 +129,7 @@ define void @test_vst2_fx_update(i64** %ptr, <1 x i64> %B) nounwind { define void @test_vst2_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind { ; CHECK: test_vst2_reg_update -; CHECK: st2 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st2 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}], x{{[0-9]+}} %A = load i8** %ptr call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %B, <8 x i8> %B, i32 4) %tmp0 = getelementptr i8* %A, i32 %inc @@ -139,7 +139,7 @@ define void @test_vst2_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind { define void @test_vst3_fx_update(i32** %ptr, <2 x i32> %B) nounwind { ; CHECK: test_vst3_fx_update -; CHECK: st3 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}], #24 +; CHECK: st3 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}], #24 %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %B, <2 x i32> %B, <2 x i32> %B, i32 4) @@ -150,7 +150,7 @@ define void @test_vst3_fx_update(i32** %ptr, <2 x i32> %B) nounwind { define void @test_vst3_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind { ; CHECK: test_vst3_reg_update -; CHECK: st3 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [{{x[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st3 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [{{x[0-9]+|sp}}], x{{[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %B, <8 x i16> %B, <8 x i16> %B, i32 2) @@ -161,7 +161,7 @@ define void @test_vst3_reg_update(i16** %ptr, <8 x i16> %B, i32 %inc) nounwind { define void @test_vst4_fx_update(float** %ptr, <4 x float> %B) nounwind { ; CHECK: test_vst4_fx_update -; CHECK: st4 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}], #64 +; CHECK: st4 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}], #64 %A = load float** %ptr %tmp0 = bitcast float* %A to i8* call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %B, <4 x float> %B, <4 x float> %B, <4 x float> %B, i32 4) @@ -172,7 +172,7 @@ define void @test_vst4_fx_update(float** %ptr, <4 x float> %B) nounwind { define void @test_vst4_reg_update(i8** %ptr, <8 x i8> %B, i32 %inc) nounwind { ; CHECK: test_vst4_reg_update -; CHECK: st4 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [{{x[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st4 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [{{x[0-9]+|sp}}], x{{[0-9]+}} %A = load i8** %ptr call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %B, <8 x i8> %B, <8 x i8> %B, <8 x i8> %B, i32 1) %tmp0 = getelementptr i8* %A, i32 %inc @@ -201,7 +201,7 @@ declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8 define <16 x i8> @test_vld1x2_fx_update(i8* %a, i8** %ptr) { ; CHECK: test_vld1x2_fx_update -; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], #32 +; CHECK: ld1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], #32 %1 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.vld1x2.v16i8(i8* %a, i32 1) %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0 %tmp1 = getelementptr i8* %a, i32 32 @@ -211,7 +211,7 @@ define <16 x i8> @test_vld1x2_fx_update(i8* %a, i8** %ptr) { define <8 x i16> @test_vld1x2_reg_update(i16* %a, i16** %ptr, i32 %inc) { ; CHECK: test_vld1x2_reg_update -; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = bitcast i16* %a to i8* %2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x2.v8i16(i8* %1, i32 2) %3 = extractvalue { <8 x i16>, <8 x i16> } %2, 0 @@ -222,7 +222,7 @@ define <8 x i16> @test_vld1x2_reg_update(i16* %a, i16** %ptr, i32 %inc) { define <2 x i64> @test_vld1x3_fx_update(i64* %a, i64** %ptr) { ; CHECK: test_vld1x3_fx_update -; CHECK: ld1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}], #48 +; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}], #48 %1 = bitcast i64* %a to i8* %2 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.vld1x3.v2i64(i8* %1, i32 8) %3 = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } %2, 0 @@ -233,7 +233,7 @@ define <2 x i64> @test_vld1x3_fx_update(i64* %a, i64** %ptr) { define <8 x i16> @test_vld1x3_reg_update(i16* %a, i16** %ptr, i32 %inc) { ; CHECK: test_vld1x3_reg_update -; CHECK: ld1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = bitcast i16* %a to i8* %2 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.vld1x3.v8i16(i8* %1, i32 2) %3 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } %2, 0 @@ -244,7 +244,7 @@ define <8 x i16> @test_vld1x3_reg_update(i16* %a, i16** %ptr, i32 %inc) { define <4 x float> @test_vld1x4_fx_update(float* %a, float** %ptr) { ; CHECK: test_vld1x4_fx_update -; CHECK: ld1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #64 +; CHECK: ld1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], #64 %1 = bitcast float* %a to i8* %2 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.vld1x4.v4f32(i8* %1, i32 4) %3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %2, 0 @@ -255,7 +255,7 @@ define <4 x float> @test_vld1x4_fx_update(float* %a, float** %ptr) { define <8 x i8> @test_vld1x4_reg_update(i8* readonly %a, i8** %ptr, i32 %inc) #0 { ; CHECK: test_vld1x4_reg_update -; CHECK: ld1 {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld1 { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.vld1x4.v8i8(i8* %a, i32 1) %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %1, 0 %tmp1 = getelementptr i8* %a, i32 %inc @@ -265,7 +265,7 @@ define <8 x i8> @test_vld1x4_reg_update(i8* readonly %a, i8** %ptr, i32 %inc) #0 define void @test_vst1x2_fx_update(i8* %a, [2 x <16 x i8>] %b.coerce, i8** %ptr) #2 { ; CHECK: test_vst1x2_fx_update -; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], #32 +; CHECK: st1 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], #32 %1 = extractvalue [2 x <16 x i8>] %b.coerce, 0 %2 = extractvalue [2 x <16 x i8>] %b.coerce, 1 tail call void @llvm.aarch64.neon.vst1x2.v16i8(i8* %a, <16 x i8> %1, <16 x i8> %2, i32 1) @@ -276,7 +276,7 @@ define void @test_vst1x2_fx_update(i8* %a, [2 x <16 x i8>] %b.coerce, i8** %ptr) define void @test_vst1x2_reg_update(i16* %a, [2 x <8 x i16>] %b.coerce, i16** %ptr, i32 %inc) #2 { ; CHECK: test_vst1x2_reg_update -; CHECK: st1 {v{{[0-9]+}}.8h, v{{[0-9]+}}.8h}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st1 { v{{[0-9]+}}.8h, v{{[0-9]+}}.8h }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [2 x <8 x i16>] %b.coerce, 0 %2 = extractvalue [2 x <8 x i16>] %b.coerce, 1 %3 = bitcast i16* %a to i8* @@ -288,7 +288,7 @@ define void @test_vst1x2_reg_update(i16* %a, [2 x <8 x i16>] %b.coerce, i16** %p define void @test_vst1x3_fx_update(i32* %a, [3 x <2 x i32>] %b.coerce, i32** %ptr) #2 { ; CHECK: test_vst1x3_fx_update -; CHECK: st1 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #24 +; CHECK: st1 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], #24 %1 = extractvalue [3 x <2 x i32>] %b.coerce, 0 %2 = extractvalue [3 x <2 x i32>] %b.coerce, 1 %3 = extractvalue [3 x <2 x i32>] %b.coerce, 2 @@ -301,7 +301,7 @@ define void @test_vst1x3_fx_update(i32* %a, [3 x <2 x i32>] %b.coerce, i32** %pt define void @test_vst1x3_reg_update(i64* %a, [3 x <1 x i64>] %b.coerce, i64** %ptr, i32 %inc) #2 { ; CHECK: test_vst1x3_reg_update -; CHECK: st1 {v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st1 { v{{[0-9]+}}.1d, v{{[0-9]+}}.1d, v{{[0-9]+}}.1d }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [3 x <1 x i64>] %b.coerce, 0 %2 = extractvalue [3 x <1 x i64>] %b.coerce, 1 %3 = extractvalue [3 x <1 x i64>] %b.coerce, 2 @@ -314,7 +314,7 @@ define void @test_vst1x3_reg_update(i64* %a, [3 x <1 x i64>] %b.coerce, i64** %p define void @test_vst1x4_fx_update(float* %a, [4 x <4 x float>] %b.coerce, float** %ptr) #2 { ; CHECK: test_vst1x4_fx_update -; CHECK: st1 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], #64 +; CHECK: st1 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], #64 %1 = extractvalue [4 x <4 x float>] %b.coerce, 0 %2 = extractvalue [4 x <4 x float>] %b.coerce, 1 %3 = extractvalue [4 x <4 x float>] %b.coerce, 2 @@ -328,7 +328,7 @@ define void @test_vst1x4_fx_update(float* %a, [4 x <4 x float>] %b.coerce, float define void @test_vst1x4_reg_update(double* %a, [4 x <2 x double>] %b.coerce, double** %ptr, i32 %inc) #2 { ; CHECK: test_vst1x4_reg_update -; CHECK: st1 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [4 x <2 x double>] %b.coerce, 0 %2 = extractvalue [4 x <2 x double>] %b.coerce, 1 %3 = extractvalue [4 x <2 x double>] %b.coerce, 2 diff --git a/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll b/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll index 80a934700c..e53d6cb339 100644 --- a/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll +++ b/test/CodeGen/AArch64/neon-simd-post-ldst-one.ll @@ -2,7 +2,7 @@ define { [2 x <16 x i8>] } @test_vld2q_dup_fx_update(i8* %a, i8** %ptr) { ; CHECK-LABEL: test_vld2q_dup_fx_update -; CHECK: ld2r {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [x{{[0-9]+|sp}}], #2 +; CHECK: ld2r { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [x{{[0-9]+|sp}}], #2 %1 = tail call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2lane.v16i8(i8* %a, <16 x i8> undef, <16 x i8> undef, i32 0, i32 1) %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0 %3 = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer @@ -17,7 +17,7 @@ define { [2 x <16 x i8>] } @test_vld2q_dup_fx_update(i8* %a, i8** %ptr) { define { [2 x <4 x i32>] } @test_vld2q_dup_reg_update(i32* %a, i32** %ptr, i32 %inc) { ; CHECK-LABEL: test_vld2q_dup_reg_update -; CHECK: ld2r {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld2r { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = bitcast i32* %a to i8* %2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8* %1, <4 x i32> undef, <4 x i32> undef, i32 0, i32 4) %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 0 @@ -33,7 +33,7 @@ define { [2 x <4 x i32>] } @test_vld2q_dup_reg_update(i32* %a, i32** %ptr, i32 % define { [3 x <4 x i16>] } @test_vld3_dup_fx_update(i16* %a, i16** %ptr) { ; CHECK-LABEL: test_vld3_dup_fx_update -; CHECK: ld3r {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [x{{[0-9]+|sp}}], #6 +; CHECK: ld3r { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [x{{[0-9]+|sp}}], #6 %1 = bitcast i16* %a to i8* %2 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3lane.v4i16(i8* %1, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2) %3 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %2, 0 @@ -52,7 +52,7 @@ define { [3 x <4 x i16>] } @test_vld3_dup_fx_update(i16* %a, i16** %ptr) { define { [3 x <8 x i8>] } @test_vld3_dup_reg_update(i8* %a, i8** %ptr, i32 %inc) { ; CHECK-LABEL: test_vld3_dup_reg_update -; CHECK: ld3r {v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld3r { v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3lane.v8i8(i8* %a, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) %2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %1, 0 %3 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer @@ -70,7 +70,7 @@ define { [3 x <8 x i8>] } @test_vld3_dup_reg_update(i8* %a, i8** %ptr, i32 %inc) define { [4 x <2 x i32>] } @test_vld4_dup_fx_update(i32* %a, i32** %ptr) #0 { ; CHECK-LABEL: test_vld4_dup_fx_update -; CHECK: ld4r {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [x{{[0-9]+|sp}}], #16 +; CHECK: ld4r { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [x{{[0-9]+|sp}}], #16 %1 = bitcast i32* %a to i8* %2 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld4lane.v2i32(i8* %1, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 4) %3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %2, 0 @@ -92,7 +92,7 @@ define { [4 x <2 x i32>] } @test_vld4_dup_fx_update(i32* %a, i32** %ptr) #0 { define { [4 x <2 x double>] } @test_vld4_dup_reg_update(double* %a, double** %ptr, i32 %inc) { ; CHECK-LABEL: test_vld4_dup_reg_update -; CHECK: ld4r {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld4r { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = bitcast double* %a to i8* %2 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm.neon.vld4lane.v2f64(i8* %1, <2 x double> undef, <2 x double> undef, <2 x double> undef, <2 x double> undef, i32 0, i32 8) %3 = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %2, 0 @@ -114,7 +114,7 @@ define { [4 x <2 x double>] } @test_vld4_dup_reg_update(double* %a, double** %pt define { [2 x <8 x i8>] } @test_vld2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr) { ; CHECK-LABEL: test_vld2_lane_fx_update -; CHECK: ld2 {v{{[0-9]+}}.b, v{{[0-9]+}}.b}[7], [x{{[0-9]+|sp}}], #2 +; CHECK: ld2 { v{{[0-9]+}}.b, v{{[0-9]+}}.b }[7], [x{{[0-9]+|sp}}], #2 %1 = extractvalue [2 x <8 x i8>] %b, 0 %2 = extractvalue [2 x <8 x i8>] %b, 1 %3 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 7, i32 1) @@ -129,7 +129,7 @@ define { [2 x <8 x i8>] } @test_vld2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, define { [2 x <8 x i8>] } @test_vld2_lane_reg_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr, i32 %inc) { ; CHECK-LABEL: test_vld2_lane_reg_update -; CHECK: ld2 {v{{[0-9]+}}.b, v{{[0-9]+}}.b}[6], [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld2 { v{{[0-9]+}}.b, v{{[0-9]+}}.b }[6], [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [2 x <8 x i8>] %b, 0 %2 = extractvalue [2 x <8 x i8>] %b, 1 %3 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 6, i32 1) @@ -144,7 +144,7 @@ define { [2 x <8 x i8>] } @test_vld2_lane_reg_update(i8* %a, [2 x <8 x i8>] %b, define { [3 x <2 x float>] } @test_vld3_lane_fx_update(float* %a, [3 x <2 x float>] %b, float** %ptr) { ; CHECK-LABEL: test_vld3_lane_fx_update -; CHECK: ld3 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], #12 +; CHECK: ld3 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], #12 %1 = extractvalue [3 x <2 x float>] %b, 0 %2 = extractvalue [3 x <2 x float>] %b, 1 %3 = extractvalue [3 x <2 x float>] %b, 2 @@ -163,7 +163,7 @@ define { [3 x <2 x float>] } @test_vld3_lane_fx_update(float* %a, [3 x <2 x floa define { [3 x <4 x i16>] } @test_vld3_lane_reg_update(i16* %a, [3 x <4 x i16>] %b, i16** %ptr, i32 %inc) { ; CHECK-LABEL: test_vld3_lane_reg_update -; CHECK: ld3 {v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h}[3], [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld3 { v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h }[3], [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [3 x <4 x i16>] %b, 0 %2 = extractvalue [3 x <4 x i16>] %b, 1 %3 = extractvalue [3 x <4 x i16>] %b, 2 @@ -182,7 +182,7 @@ define { [3 x <4 x i16>] } @test_vld3_lane_reg_update(i16* %a, [3 x <4 x i16>] % define { [4 x <2 x i32>] } @test_vld4_lane_fx_update(i32* readonly %a, [4 x <2 x i32>] %b, i32** %ptr) { ; CHECK-LABEL: test_vld4_lane_fx_update -; CHECK: ld4 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], #16 +; CHECK: ld4 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], #16 %1 = extractvalue [4 x <2 x i32>] %b, 0 %2 = extractvalue [4 x <2 x i32>] %b, 1 %3 = extractvalue [4 x <2 x i32>] %b, 2 @@ -204,7 +204,7 @@ define { [4 x <2 x i32>] } @test_vld4_lane_fx_update(i32* readonly %a, [4 x <2 x define { [4 x <2 x double>] } @test_vld4_lane_reg_update(double* readonly %a, [4 x <2 x double>] %b, double** %ptr, i32 %inc) { ; CHECK-LABEL: test_vld4_lane_reg_update -; CHECK: ld4 {v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d}[1], [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: ld4 { v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d }[1], [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [4 x <2 x double>] %b, 0 %2 = extractvalue [4 x <2 x double>] %b, 1 %3 = extractvalue [4 x <2 x double>] %b, 2 @@ -226,7 +226,7 @@ define { [4 x <2 x double>] } @test_vld4_lane_reg_update(double* readonly %a, [4 define void @test_vst2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr) { ; CHECK-LABEL: test_vst2_lane_fx_update -; CHECK: st2 {v{{[0-9]+}}.b, v{{[0-9]+}}.b}[7], [x{{[0-9]+|sp}}], #2 +; CHECK: st2 { v{{[0-9]+}}.b, v{{[0-9]+}}.b }[7], [x{{[0-9]+|sp}}], #2 %1 = extractvalue [2 x <8 x i8>] %b, 0 %2 = extractvalue [2 x <8 x i8>] %b, 1 call void @llvm.arm.neon.vst2lane.v8i8(i8* %a, <8 x i8> %1, <8 x i8> %2, i32 7, i32 1) @@ -237,7 +237,7 @@ define void @test_vst2_lane_fx_update(i8* %a, [2 x <8 x i8>] %b, i8** %ptr) { define void @test_vst2_lane_reg_update(i32* %a, [2 x <2 x i32>] %b.coerce, i32** %ptr, i32 %inc) { ; CHECK-LABEL: test_vst2_lane_reg_update -; CHECK: st2 {v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st2 { v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [2 x <2 x i32>] %b.coerce, 0 %2 = extractvalue [2 x <2 x i32>] %b.coerce, 1 %3 = bitcast i32* %a to i8* @@ -249,7 +249,7 @@ define void @test_vst2_lane_reg_update(i32* %a, [2 x <2 x i32>] %b.coerce, i32** define void @test_vst3_lane_fx_update(float* %a, [3 x <4 x float>] %b, float** %ptr) { ; CHECK-LABEL: test_vst3_lane_fx_update -; CHECK: st3 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[3], [x{{[0-9]+|sp}}], #12 +; CHECK: st3 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[3], [x{{[0-9]+|sp}}], #12 %1 = extractvalue [3 x <4 x float>] %b, 0 %2 = extractvalue [3 x <4 x float>] %b, 1 %3 = extractvalue [3 x <4 x float>] %b, 2 @@ -263,7 +263,7 @@ define void @test_vst3_lane_fx_update(float* %a, [3 x <4 x float>] %b, float** % ; Function Attrs: nounwind define void @test_vst3_lane_reg_update(i16* %a, [3 x <4 x i16>] %b, i16** %ptr, i32 %inc) { ; CHECK-LABEL: test_vst3_lane_reg_update -; CHECK: st3 {v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h}[3], [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st3 { v{{[0-9]+}}.h, v{{[0-9]+}}.h, v{{[0-9]+}}.h }[3], [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [3 x <4 x i16>] %b, 0 %2 = extractvalue [3 x <4 x i16>] %b, 1 %3 = extractvalue [3 x <4 x i16>] %b, 2 @@ -276,7 +276,7 @@ define void @test_vst3_lane_reg_update(i16* %a, [3 x <4 x i16>] %b, i16** %ptr, define void @test_vst4_lane_fx_update(double* %a, [4 x <2 x double>] %b.coerce, double** %ptr) { ; CHECK-LABEL: test_vst4_lane_fx_update -; CHECK: st4 {v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d}[1], [x{{[0-9]+|sp}}], #32 +; CHECK: st4 { v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d, v{{[0-9]+}}.d }[1], [x{{[0-9]+|sp}}], #32 %1 = extractvalue [4 x <2 x double>] %b.coerce, 0 %2 = extractvalue [4 x <2 x double>] %b.coerce, 1 %3 = extractvalue [4 x <2 x double>] %b.coerce, 2 @@ -291,7 +291,7 @@ define void @test_vst4_lane_fx_update(double* %a, [4 x <2 x double>] %b.coerce, define void @test_vst4_lane_reg_update(float* %a, [4 x <2 x float>] %b.coerce, float** %ptr, i32 %inc) { ; CHECK-LABEL: test_vst4_lane_reg_update -; CHECK: st4 {v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s}[1], [x{{[0-9]+|sp}}], x{{[0-9]+}} +; CHECK: st4 { v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s, v{{[0-9]+}}.s }[1], [x{{[0-9]+|sp}}], x{{[0-9]+}} %1 = extractvalue [4 x <2 x float>] %b.coerce, 0 %2 = extractvalue [4 x <2 x float>] %b.coerce, 1 %3 = extractvalue [4 x <2 x float>] %b.coerce, 2 diff --git a/test/CodeGen/AArch64/neon-simd-tbl.ll b/test/CodeGen/AArch64/neon-simd-tbl.ll index 327e7f6171..53924923f7 100644 --- a/test/CodeGen/AArch64/neon-simd-tbl.ll +++ b/test/CodeGen/AArch64/neon-simd-tbl.ll @@ -37,7 +37,7 @@ declare <8 x i8> @llvm.aarch64.neon.vtbl3.v8i8(<16 x i8>, <16 x i8>, <16 x i8>, define <8 x i8> @test_vtbl1_s8(<8 x i8> %a, <8 x i8> %b) { ; CHECK: test_vtbl1_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %b) @@ -46,7 +46,7 @@ entry: define <8 x i8> @test_vqtbl1_s8(<16 x i8> %a, <8 x i8> %b) { ; CHECK: test_vqtbl1_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %a, <8 x i8> %b) ret <8 x i8> %vtbl1.i @@ -54,7 +54,7 @@ entry: define <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl2_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 1 @@ -65,7 +65,7 @@ entry: define <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl2_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1 @@ -75,7 +75,7 @@ entry: define <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl3_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 1 @@ -88,7 +88,7 @@ entry: define <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl3_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1 @@ -99,7 +99,7 @@ entry: define <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl4_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 1 @@ -113,7 +113,7 @@ entry: define <8 x i8> @test_vqtbl4_s8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl4_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1 @@ -125,7 +125,7 @@ entry: define <16 x i8> @test_vqtbl1q_s8(<16 x i8> %a, <16 x i8> %b) { ; CHECK: test_vqtbl1q_s8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %vtbl1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbl1.v16i8(<16 x i8> %a, <16 x i8> %b) ret <16 x i8> %vtbl1.i @@ -133,7 +133,7 @@ entry: define <16 x i8> @test_vqtbl2q_s8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl2q_s8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1 @@ -143,7 +143,7 @@ entry: define <16 x i8> @test_vqtbl3q_s8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl3q_s8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1 @@ -154,7 +154,7 @@ entry: define <16 x i8> @test_vqtbl4q_s8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl4q_s8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1 @@ -166,7 +166,7 @@ entry: define <8 x i8> @test_vtbx1_s8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK: test_vtbx1_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %c) @@ -178,7 +178,7 @@ entry: define <8 x i8> @test_vtbx2_s8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx2_s8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 1 @@ -189,7 +189,7 @@ entry: define <8 x i8> @test_vtbx3_s8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx3_s8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 1 @@ -205,7 +205,7 @@ entry: define <8 x i8> @test_vtbx4_s8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx4_s8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 1 @@ -219,7 +219,7 @@ entry: define <8 x i8> @test_vqtbx1_s8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) { ; CHECK: test_vqtbx1_s8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbx1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) ret <8 x i8> %vtbx1.i @@ -227,7 +227,7 @@ entry: define <8 x i8> @test_vqtbx2_s8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx2_s8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -237,7 +237,7 @@ entry: define <8 x i8> @test_vqtbx3_s8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx3_s8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -248,7 +248,7 @@ entry: define <8 x i8> @test_vqtbx4_s8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx4_s8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -260,7 +260,7 @@ entry: define <16 x i8> @test_vqtbx1q_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { ; CHECK: test_vqtbx1q_s8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %vtbx1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) ret <16 x i8> %vtbx1.i @@ -268,7 +268,7 @@ entry: define <16 x i8> @test_vqtbx2q_s8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx2q_s8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -278,7 +278,7 @@ entry: define <16 x i8> @test_vqtbx3q_s8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx3q_s8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -289,7 +289,7 @@ entry: define <16 x i8> @test_vqtbx4q_s8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx4q_s8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -301,7 +301,7 @@ entry: define <8 x i8> @test_vtbl1_u8(<8 x i8> %a, <8 x i8> %b) { ; CHECK: test_vtbl1_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %b) @@ -310,7 +310,7 @@ entry: define <8 x i8> @test_vqtbl1_u8(<16 x i8> %a, <8 x i8> %b) { ; CHECK: test_vqtbl1_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %a, <8 x i8> %b) ret <8 x i8> %vtbl1.i @@ -318,7 +318,7 @@ entry: define <8 x i8> @test_vtbl2_u8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl2_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 1 @@ -329,7 +329,7 @@ entry: define <8 x i8> @test_vqtbl2_u8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl2_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1 @@ -339,7 +339,7 @@ entry: define <8 x i8> @test_vtbl3_u8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl3_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 1 @@ -352,7 +352,7 @@ entry: define <8 x i8> @test_vqtbl3_u8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl3_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1 @@ -363,7 +363,7 @@ entry: define <8 x i8> @test_vtbl4_u8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl4_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 1 @@ -377,7 +377,7 @@ entry: define <8 x i8> @test_vqtbl4_u8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl4_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1 @@ -389,7 +389,7 @@ entry: define <16 x i8> @test_vqtbl1q_u8(<16 x i8> %a, <16 x i8> %b) { ; CHECK: test_vqtbl1q_u8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %vtbl1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbl1.v16i8(<16 x i8> %a, <16 x i8> %b) ret <16 x i8> %vtbl1.i @@ -397,7 +397,7 @@ entry: define <16 x i8> @test_vqtbl2q_u8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl2q_u8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1 @@ -407,7 +407,7 @@ entry: define <16 x i8> @test_vqtbl3q_u8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl3q_u8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1 @@ -418,7 +418,7 @@ entry: define <16 x i8> @test_vqtbl4q_u8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl4q_u8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1 @@ -430,7 +430,7 @@ entry: define <8 x i8> @test_vtbx1_u8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK: test_vtbx1_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %c) @@ -442,7 +442,7 @@ entry: define <8 x i8> @test_vtbx2_u8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx2_u8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 1 @@ -453,7 +453,7 @@ entry: define <8 x i8> @test_vtbx3_u8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx3_u8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 1 @@ -469,7 +469,7 @@ entry: define <8 x i8> @test_vtbx4_u8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx4_u8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 1 @@ -483,7 +483,7 @@ entry: define <8 x i8> @test_vqtbx1_u8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) { ; CHECK: test_vqtbx1_u8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbx1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) ret <8 x i8> %vtbx1.i @@ -491,7 +491,7 @@ entry: define <8 x i8> @test_vqtbx2_u8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx2_u8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -501,7 +501,7 @@ entry: define <8 x i8> @test_vqtbx3_u8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx3_u8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -512,7 +512,7 @@ entry: define <8 x i8> @test_vqtbx4_u8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx4_u8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -524,7 +524,7 @@ entry: define <16 x i8> @test_vqtbx1q_u8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { ; CHECK: test_vqtbx1q_u8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %vtbx1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) ret <16 x i8> %vtbx1.i @@ -532,7 +532,7 @@ entry: define <16 x i8> @test_vqtbx2q_u8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx2q_u8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -542,7 +542,7 @@ entry: define <16 x i8> @test_vqtbx3q_u8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx3q_u8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -553,7 +553,7 @@ entry: define <16 x i8> @test_vqtbx4q_u8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx4q_u8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -565,7 +565,7 @@ entry: define <8 x i8> @test_vtbl1_p8(<8 x i8> %a, <8 x i8> %b) { ; CHECK: test_vtbl1_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %b) @@ -574,7 +574,7 @@ entry: define <8 x i8> @test_vqtbl1_p8(<16 x i8> %a, <8 x i8> %b) { ; CHECK: test_vqtbl1_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %a, <8 x i8> %b) ret <8 x i8> %vtbl1.i @@ -582,7 +582,7 @@ entry: define <8 x i8> @test_vtbl2_p8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl2_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %a.coerce, 1 @@ -593,7 +593,7 @@ entry: define <8 x i8> @test_vqtbl2_p8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl2_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1 @@ -603,7 +603,7 @@ entry: define <8 x i8> @test_vtbl3_p8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl3_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %a.coerce, 1 @@ -616,7 +616,7 @@ entry: define <8 x i8> @test_vqtbl3_p8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl3_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1 @@ -627,7 +627,7 @@ entry: define <8 x i8> @test_vtbl4_p8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vtbl4_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %a.coerce, 1 @@ -641,7 +641,7 @@ entry: define <8 x i8> @test_vqtbl4_p8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) { ; CHECK: test_vqtbl4_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1 @@ -653,7 +653,7 @@ entry: define <16 x i8> @test_vqtbl1q_p8(<16 x i8> %a, <16 x i8> %b) { ; CHECK: test_vqtbl1q_p8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %vtbl1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbl1.v16i8(<16 x i8> %a, <16 x i8> %b) ret <16 x i8> %vtbl1.i @@ -661,7 +661,7 @@ entry: define <16 x i8> @test_vqtbl2q_p8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl2q_p8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %a.coerce, 1 @@ -671,7 +671,7 @@ entry: define <16 x i8> @test_vqtbl3q_p8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl3q_p8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %a.coerce, 1 @@ -682,7 +682,7 @@ entry: define <16 x i8> @test_vqtbl4q_p8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) { ; CHECK: test_vqtbl4q_p8: -; CHECK: tbl {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbl {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__a.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 0 %__a.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %a.coerce, 1 @@ -694,7 +694,7 @@ entry: define <8 x i8> @test_vtbx1_p8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK: test_vtbx1_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbl1.i = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.vtbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %c) @@ -706,7 +706,7 @@ entry: define <8 x i8> @test_vtbx2_p8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx2_p8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <8 x i8>] %b.coerce, 1 @@ -717,7 +717,7 @@ entry: define <8 x i8> @test_vtbx3_p8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx3_p8: -; CHECK: tbl {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbl {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <8 x i8>] %b.coerce, 1 @@ -733,7 +733,7 @@ entry: define <8 x i8> @test_vtbx4_p8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vtbx4_p8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <8 x i8>] %b.coerce, 1 @@ -747,7 +747,7 @@ entry: define <8 x i8> @test_vqtbx1_p8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) { ; CHECK: test_vqtbx1_p8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %vtbx1.i = tail call <8 x i8> @llvm.aarch64.neon.vtbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) ret <8 x i8> %vtbx1.i @@ -755,7 +755,7 @@ entry: define <8 x i8> @test_vqtbx2_p8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx2_p8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -765,7 +765,7 @@ entry: define <8 x i8> @test_vqtbx3_p8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx3_p8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -776,7 +776,7 @@ entry: define <8 x i8> @test_vqtbx4_p8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) { ; CHECK: test_vqtbx4_p8: -; CHECK: tbx {{v[0-9]+}}.8b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.8b +; CHECK: tbx {{v[0-9]+}}.8b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.8b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1 @@ -788,7 +788,7 @@ entry: define <16 x i8> @test_vqtbx1q_p8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { ; CHECK: test_vqtbx1q_p8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %vtbx1.i = tail call <16 x i8> @llvm.aarch64.neon.vtbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) ret <16 x i8> %vtbx1.i @@ -796,7 +796,7 @@ entry: define <16 x i8> @test_vqtbx2q_p8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx2q_p8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [2 x <16 x i8>] %b.coerce, 1 @@ -806,7 +806,7 @@ entry: define <16 x i8> @test_vqtbx3q_p8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx3q_p8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [3 x <16 x i8>] %b.coerce, 1 @@ -817,7 +817,7 @@ entry: define <16 x i8> @test_vqtbx4q_p8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) { ; CHECK: test_vqtbx4q_p8: -; CHECK: tbx {{v[0-9]+}}.16b, {{{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b}, {{v[0-9]+}}.16b +; CHECK: tbx {{v[0-9]+}}.16b, { {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b }, {{v[0-9]+}}.16b entry: %__b.coerce.fca.0.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 0 %__b.coerce.fca.1.extract.i = extractvalue [4 x <16 x i8>] %b.coerce, 1 diff --git a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll index b2f6827113..dbaccacdf5 100644 --- a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll +++ b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll @@ -6,7 +6,7 @@ define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) { ; CHECK-LABEL: truncStore.v2i64: ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d -; CHECK: {{st1 {v[0-9]+.2s}|str d[0-9]+}}, [x{{[0-9]+|sp}}] +; CHECK: {{st1 { v[0-9]+.2s }|str d[0-9]+}}, [x{{[0-9]+|sp}}] %b = trunc <2 x i64> %a to <2 x i32> store <2 x i32> %b, <2 x i32>* %result ret void @@ -15,7 +15,7 @@ define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) { define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) { ; CHECK-LABEL: truncStore.v4i32: ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s -; CHECK: {{st1 {v[0-9]+.4h}|str d[0-9]+}}, [x{{[0-9]+|sp}}] +; CHECK: {{st1 { v[0-9]+.4h }|str d[0-9]+}}, [x{{[0-9]+|sp}}] %b = trunc <4 x i32> %a to <4 x i16> store <4 x i16> %b, <4 x i16>* %result ret void @@ -24,7 +24,7 @@ define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) { define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) { ; CHECK-LABEL: truncStore.v8i16: ; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h -; CHECK: {{st1 {v[0-9]+.8b}|str d[0-9]+}}, [x{{[0-9]+|sp}}] +; CHECK: {{st1 { v[0-9]+.8b }|str d[0-9]+}}, [x{{[0-9]+|sp}}] %b = trunc <8 x i16> %a to <8 x i8> store <8 x i8> %b, <8 x i8>* %result ret void diff --git a/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll b/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll index 2e3f7bff02..60cc6e40b3 100644 --- a/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll +++ b/test/CodeGen/AArch64/unaligned-vector-ld1-st1.ll @@ -9,14 +9,14 @@ define <16 x i8> @qwordint (<16 x i8>* %head.v16i8, <8 x i16>* %head.v8i16, <4 x i32>* %head.v4i32, <2 x i64>* %head.v2i64, <16 x i8>* %tail.v16i8, <8 x i16>* %tail.v8i16, <4 x i32>* %tail.v4i32, <2 x i64>* %tail.v2i64) { ; CHECK-LABEL: qwordint -; CHECK: ld1 {v0.16b}, [x0] -; CHECK: ld1 {v1.8h}, [x1] -; CHECK: ld1 {v2.4s}, [x2] -; CHECK: ld1 {v3.2d}, [x3] -; CHECK: st1 {v0.16b}, [x4] -; CHECK: st1 {v1.8h}, [x5] -; CHECK: st1 {v2.4s}, [x6] -; CHECK: st1 {v3.2d}, [x7] +; CHECK: ld1 { v0.16b }, [x0] +; CHECK: ld1 { v1.8h }, [x1] +; CHECK: ld1 { v2.4s }, [x2] +; CHECK: ld1 { v3.2d }, [x3] +; CHECK: st1 { v0.16b }, [x4] +; CHECK: st1 { v1.8h }, [x5] +; CHECK: st1 { v2.4s }, [x6] +; CHECK: st1 { v3.2d }, [x7] ; BE-STRICT-ALIGN-LABEL: qwordint ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh @@ -42,10 +42,10 @@ entry: define <4 x float> @qwordfloat (<4 x float>* %head.v4f32, <2 x double>* %head.v2f64, <4 x float>* %tail.v4f32, <2 x double>* %tail.v2f64) { ; CHECK-LABEL: qwordfloat -; CHECK: ld1 {v0.4s}, [x0] -; CHECK: ld1 {v1.2d}, [x1] -; CHECK: st1 {v0.4s}, [x2] -; CHECK: st1 {v1.2d}, [x3] +; CHECK: ld1 { v0.4s }, [x0] +; CHECK: ld1 { v1.2d }, [x1] +; CHECK: st1 { v0.4s }, [x2] +; CHECK: st1 { v1.2d }, [x3] ; BE-STRICT-ALIGN-LABEL: qwordfloat ; BE-STRICT-ALIGN: ldr ; BE-STRICT-ALIGN: ldr @@ -63,23 +63,23 @@ entry: define <8 x i8> @dwordint (<8 x i8>* %head.v8i8, <4 x i16>* %head.v4i16, <2 x i32>* %head.v2i32, <1 x i64>* %head.v1i64, <8 x i8>* %tail.v8i8, <4 x i16>* %tail.v4i16, <2 x i32>* %tail.v2i32, <1 x i64>* %tail.v1i64) { ; CHECK-LABEL: dwordint -; CHECK: ld1 {v0.8b}, [x0] -; CHECK: ld1 {v1.4h}, [x1] -; CHECK: ld1 {v2.2s}, [x2] -; CHECK: ld1 {v3.1d}, [x3] -; CHECK: st1 {v0.8b}, [x4] -; CHECK: st1 {v1.4h}, [x5] -; CHECK: st1 {v2.2s}, [x6] -; CHECK: st1 {v3.1d}, [x7] +; CHECK: ld1 { v0.8b }, [x0] +; CHECK: ld1 { v1.4h }, [x1] +; CHECK: ld1 { v2.2s }, [x2] +; CHECK: ld1 { v3.1d }, [x3] +; CHECK: st1 { v0.8b }, [x4] +; CHECK: st1 { v1.4h }, [x5] +; CHECK: st1 { v2.2s }, [x6] +; CHECK: st1 { v3.1d }, [x7] ; BE-STRICT-ALIGN-LABEL: dwordint ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh ; BE-STRICT-ALIGN: ldr -; BE-STRICT-ALIGN: ld1 {v1.1d}, [x3] +; BE-STRICT-ALIGN: ld1 { v1.1d }, [x3] ; BE-STRICT-ALIGN: strb ; BE-STRICT-ALIGN: strh ; BE-STRICT-ALIGN: str -; BE-STRICT-ALIGN: st1 {v1.1d}, [x7] +; BE-STRICT-ALIGN: st1 { v1.1d }, [x7] entry: %val.v8i8 = load <8 x i8>* %head.v8i8, align 1 %val.v4i16 = load <4 x i16>* %head.v4i16, align 2 @@ -96,15 +96,15 @@ entry: define <2 x float> @dwordfloat (<2 x float>* %head.v2f32, <1 x double>* %head.v1f64, <2 x float>* %tail.v2f32, <1 x double>* %tail.v1f64) { ; CHECK-LABEL: dwordfloat -; CHECK: ld1 {v0.2s}, [x0] -; CHECK: ld1 {v1.1d}, [x1] -; CHECK: st1 {v0.2s}, [x2] -; CHECK: st1 {v1.1d}, [x3] +; CHECK: ld1 { v0.2s }, [x0] +; CHECK: ld1 { v1.1d }, [x1] +; CHECK: st1 { v0.2s }, [x2] +; CHECK: st1 { v1.1d }, [x3] ; BE-STRICT-ALIGN-LABEL: dwordfloat ; BE-STRICT-ALIGN: ldr -; BE-STRICT-ALIGN: ld1 {v1.1d}, [x1] +; BE-STRICT-ALIGN: ld1 { v1.1d }, [x1] ; BE-STRICT-ALIGN: str -; BE-STRICT-ALIGN: st1 {v1.1d}, [x3] +; BE-STRICT-ALIGN: st1 { v1.1d }, [x3] entry: %val.v2f32 = load <2 x float>* %head.v2f32, align 4 %val.v1f64 = load <1 x double>* %head.v1f64, align 8 @@ -117,14 +117,14 @@ entry: define <2 x i64> @align2vi64 (<2 x i64>* %head.byte, <2 x i64>* %head.half, <2 x i64>* %head.word, <2 x i64>* %head.dword, <2 x i64>* %tail.byte, <2 x i64>* %tail.half, <2 x i64>* %tail.word, <2 x i64>* %tail.dword) { ; CHECK-LABEL: align2vi64 -; CHECK: ld1 {v0.2d}, [x0] -; CHECK: ld1 {v1.2d}, [x1] -; CHECK: ld1 {v2.2d}, [x2] -; CHECK: ld1 {v3.2d}, [x3] -; CHECK: st1 {v0.2d}, [x4] -; CHECK: st1 {v1.2d}, [x5] -; CHECK: st1 {v2.2d}, [x6] -; CHECK: st1 {v3.2d}, [x7] +; CHECK: ld1 { v0.2d }, [x0] +; CHECK: ld1 { v1.2d }, [x1] +; CHECK: ld1 { v2.2d }, [x2] +; CHECK: ld1 { v3.2d }, [x3] +; CHECK: st1 { v0.2d }, [x4] +; CHECK: st1 { v1.2d }, [x5] +; CHECK: st1 { v2.2d }, [x6] +; CHECK: st1 { v3.2d }, [x7] ; BE-STRICT-ALIGN-LABEL: align2vi64 ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh @@ -142,18 +142,18 @@ entry: store <2 x i64> %val.word, <2 x i64>* %tail.word, align 4 store <2 x i64> %val.dword, <2 x i64>* %tail.dword, align 8 ret <2 x i64> %val.byte -} + } ;; Check load/store of 64-bit vectors with less-than 8-byte alignment define <2 x float> @align2vf32 (<2 x float>* %head.byte, <2 x float>* %head.half, <2 x float>* %head.word, <2 x float>* %head.dword, <2 x float>* %tail.byte, <2 x float>* %tail.half, <2 x float>* %tail.word, <2 x float>* %tail.dword) { ; CHECK-LABEL: align2vf32 -; CHECK: ld1 {v0.2s}, [x0] -; CHECK: ld1 {v1.2s}, [x1] -; CHECK: ld1 {v2.2s}, [x2] -; CHECK: st1 {v0.2s}, [x4] -; CHECK: st1 {v1.2s}, [x5] -; CHECK: st1 {v2.2s}, [x6] +; CHECK: ld1 { v0.2s }, [x0] +; CHECK: ld1 { v1.2s }, [x1] +; CHECK: ld1 { v2.2s }, [x2] +; CHECK: st1 { v0.2s }, [x4] +; CHECK: st1 { v1.2s }, [x5] +; CHECK: st1 { v2.2s }, [x6] ; BE-STRICT-ALIGN-LABEL: align2vf32 ; BE-STRICT-ALIGN: ldrb ; BE-STRICT-ALIGN: ldrh |