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path: root/test/CodeGen/CellSPU/fneg-fabs.ll
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-rw-r--r--test/CodeGen/CellSPU/fneg-fabs.ll8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/CellSPU/fneg-fabs.ll b/test/CodeGen/CellSPU/fneg-fabs.ll
index 4c6fbb95a3..5bd66f4aae 100644
--- a/test/CodeGen/CellSPU/fneg-fabs.ll
+++ b/test/CodeGen/CellSPU/fneg-fabs.ll
@@ -7,22 +7,22 @@ target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i
target triple = "spu"
define double @fneg_dp(double %X) {
- %Y = sub double -0.000000e+00, %X
+ %Y = fsub double -0.000000e+00, %X
ret double %Y
}
define <2 x double> @fneg_dp_vec(<2 x double> %X) {
- %Y = sub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X
+ %Y = fsub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X
ret <2 x double> %Y
}
define float @fneg_sp(float %X) {
- %Y = sub float -0.000000e+00, %X
+ %Y = fsub float -0.000000e+00, %X
ret float %Y
}
define <4 x float> @fneg_sp_vec(<4 x float> %X) {
- %Y = sub <4 x float> <float -0.000000e+00, float -0.000000e+00,
+ %Y = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00, float -0.000000e+00>, %X
ret <4 x float> %Y
}