summaryrefslogtreecommitdiff
path: root/test/CodeGen/Hexagon
diff options
context:
space:
mode:
Diffstat (limited to 'test/CodeGen/Hexagon')
-rw-r--r--test/CodeGen/Hexagon/BranchPredict.ll79
-rw-r--r--test/CodeGen/Hexagon/args.ll9
-rw-r--r--test/CodeGen/Hexagon/extload-combine.ll80
-rw-r--r--test/CodeGen/Hexagon/packetize_cond_inst.ll32
-rw-r--r--test/CodeGen/Hexagon/tfr-to-combine.ll35
5 files changed, 229 insertions, 6 deletions
diff --git a/test/CodeGen/Hexagon/BranchPredict.ll b/test/CodeGen/Hexagon/BranchPredict.ll
new file mode 100644
index 0000000000..716e85da5a
--- /dev/null
+++ b/test/CodeGen/Hexagon/BranchPredict.ll
@@ -0,0 +1,79 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+
+; Check if the branch probabilities are reflected in the instructions:
+; The basic block placement pass should place the more probable successor
+; block as the fall-through block. The unconditional jump in the predecessor
+; should then get the right hint (not_taken or ":nt")
+
+
+@j = external global i32
+
+define i32 @foo(i32 %a) nounwind {
+; CHECK: if{{ *}}(!p{{[0-3]}}.new) jump:nt
+entry:
+ %tobool = icmp eq i32 %a, 0
+ br i1 %tobool, label %if.else, label %if.then, !prof !0
+
+if.then: ; preds = %entry
+ %add = add nsw i32 %a, 10
+ %call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind
+ br label %return
+
+if.else: ; preds = %entry
+ %call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 4) nounwind
+ br label %return
+
+return: ; preds = %if.else, %if.then
+ %retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %retval.0
+}
+
+declare i32 @foobar(...)
+
+define i32 @bar(i32 %a) nounwind {
+; CHECK: if{{ *}}(p{{[0-3]}}.new) jump:nt
+entry:
+ %tobool = icmp eq i32 %a, 0
+ br i1 %tobool, label %if.else, label %if.then, !prof !1
+
+if.then: ; preds = %entry
+ %add = add nsw i32 %a, 10
+ %call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind
+ br label %return
+
+if.else: ; preds = %entry
+ %call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 4) nounwind
+ br label %return
+
+return: ; preds = %if.else, %if.then
+ %retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %retval.0
+}
+
+define i32 @foo_bar(i32 %a, i16 signext %b) nounwind {
+; CHECK: if{{ *}}(!cmp.eq(r{{[0-9]*}}.new, #0)) jump:nt
+entry:
+ %0 = load i32* @j, align 4, !tbaa !2
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %if.else, label %if.then, !prof !0
+
+if.then: ; preds = %entry
+ %add = add nsw i32 %a, 10
+ %call = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add) nounwind
+ br label %return
+
+if.else: ; preds = %entry
+ %add1 = add nsw i32 %a, 4
+ %call2 = tail call i32 bitcast (i32 (...)* @foobar to i32 (i32)*)(i32 %add1) nounwind
+ br label %return
+
+return: ; preds = %if.else, %if.then
+ %retval.0 = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %retval.0
+}
+
+!0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
+!1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
+!2 = metadata !{metadata !"int", metadata !3}
+!3 = metadata !{metadata !"omnipotent char", metadata !4}
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/Hexagon/args.ll b/test/CodeGen/Hexagon/args.ll
index f8c9e44c83..aea4ffe2ee 100644
--- a/test/CodeGen/Hexagon/args.ll
+++ b/test/CodeGen/Hexagon/args.ll
@@ -1,11 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
-; CHECK: r0 = #1
-; CHECK: r1 = #2
-; CHECK: r2 = #3
-; CHECK: r3 = #4
-; CHECK: r4 = #5
-; CHECK: r5 = #6
+; CHECK: r1:0 = combine(#2, #1)
+; CHECK: r3:2 = combine(#4, #3)
+; CHECK: r5:4 = combine(#6, #5)
define void @foo() nounwind {
diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll
new file mode 100644
index 0000000000..b3b8bf0703
--- /dev/null
+++ b/test/CodeGen/Hexagon/extload-combine.ll
@@ -0,0 +1,80 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
+; Check that the combine/stxw instructions are being generated.
+; In case of combine one of the operand should be 0 and another should be
+; the output of absolute addressing load instruction.
+
+@a = external global i16
+@b = external global i16
+@c = external global i16
+@char_a = external global i8
+@char_b = external global i8
+@char_c = external global i8
+@int_a = external global i32
+@int_b = external global i32
+@int_c = external global i32
+
+; Function Attrs: nounwind
+define i64 @short_test1() #0 {
+; CHECK: [[VAR:r[0-9]+]]{{ *}}={{ *}}memuh(##
+; CHECK: combine(#0, [[VAR]])
+entry:
+ store i16 0, i16* @a, align 2
+ %0 = load i16* @b, align 2
+ %conv2 = zext i16 %0 to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: nounwind
+define i64 @short_test2() #0 {
+; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(##
+; CHECK: sxtw([[VAR1]])
+entry:
+ store i16 0, i16* @a, align 2
+ %0 = load i16* @c, align 2
+ %conv2 = sext i16 %0 to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: nounwind
+define i64 @char_test1() #0 {
+; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(##
+; CHECK: combine(#0, [[VAR2]])
+entry:
+ store i8 0, i8* @char_a, align 1
+ %0 = load i8* @char_b, align 1
+ %conv2 = zext i8 %0 to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: nounwind
+define i64 @char_test2() #0 {
+; CHECK: [[VAR3:r[0-9]+]]{{ *}}={{ *}}memb(##
+; CHECK: sxtw([[VAR3]])
+entry:
+ store i8 0, i8* @char_a, align 1
+ %0 = load i8* @char_c, align 1
+ %conv2 = sext i8 %0 to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: nounwind
+define i64 @int_test1() #0 {
+; CHECK: [[VAR4:r[0-9]+]]{{ *}}={{ *}}memw(##
+; CHECK: combine(#0, [[VAR4]])
+entry:
+ store i32 0, i32* @int_a, align 4
+ %0 = load i32* @int_b, align 4
+ %conv = zext i32 %0 to i64
+ ret i64 %conv
+}
+
+; Function Attrs: nounwind
+define i64 @int_test2() #0 {
+; CHECK: [[VAR5:r[0-9]+]]{{ *}}={{ *}}memw(##
+; CHECK: sxtw([[VAR5]])
+entry:
+ store i32 0, i32* @int_a, align 4
+ %0 = load i32* @int_c, align 4
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
diff --git a/test/CodeGen/Hexagon/packetize_cond_inst.ll b/test/CodeGen/Hexagon/packetize_cond_inst.ll
new file mode 100644
index 0000000000..a48a9f62ec
--- /dev/null
+++ b/test/CodeGen/Hexagon/packetize_cond_inst.ll
@@ -0,0 +1,32 @@
+; RUN: llc -mcpu=hexagonv4 -tail-dup-size=1 < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon-unknown--elf"
+
+; Make sure we put the two conditionally executed adds in a packet.
+; ifcnv_add:
+; {
+; p0 = cmp.gt(r2, r1)
+; if (!p0.new) r0 = add(r2, r1)
+; if (p0.new) r0 = add(r0, #10)
+; }
+; CHECK: cmp
+; CHECK-NEXT: add
+; CHECH-NEXT: add
+define i32 @ifcnv_add(i32, i32, i32) nounwind readnone {
+ %4 = icmp sgt i32 %2, %1
+ br i1 %4, label %5, label %7
+
+; <label>:5 ; preds = %3
+ %6 = add nsw i32 %0, 10
+ br label %9
+
+; <label>:7 ; preds = %3
+ %8 = add nsw i32 %2, %1
+ br label %9
+
+; <label>:9 ; preds = %7, %5
+ %10 = phi i32 [ %6, %5 ], [ %8, %7 ]
+ %11 = add nsw i32 %10, 1
+ ret i32 %11
+}
diff --git a/test/CodeGen/Hexagon/tfr-to-combine.ll b/test/CodeGen/Hexagon/tfr-to-combine.ll
new file mode 100644
index 0000000000..e3057cd161
--- /dev/null
+++ b/test/CodeGen/Hexagon/tfr-to-combine.ll
@@ -0,0 +1,35 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
+
+; Check that we combine TFRs and TFRIs into COMBINEs.
+
+@a = external global i16
+@b = external global i16
+@c = external global i16
+
+; Function Attrs: nounwind
+define i64 @test1() #0 {
+; CHECK: combine(#10, #0)
+entry:
+ store i16 0, i16* @a, align 2
+ store i16 10, i16* @b, align 2
+ ret i64 10
+}
+
+; Function Attrs: nounwind
+define i64 @test2() #0 {
+; CHECK: combine(#0, r{{[0-9]+}})
+entry:
+ store i16 0, i16* @a, align 2
+ %0 = load i16* @c, align 2
+ %conv2 = zext i16 %0 to i64
+ ret i64 %conv2
+}
+
+; Function Attrs: nounwind
+define i64 @test4() #0 {
+; CHECK: combine(#0, ##100)
+entry:
+ store i16 100, i16* @b, align 2
+ store i16 0, i16* @a, align 2
+ ret i64 0
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-28 15:08:41 +0000