diff options
Diffstat (limited to 'test/CodeGen/R600/or.ll')
| -rw-r--r-- | test/CodeGen/R600/or.ll | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll index 3db892a362..6950ed0dfb 100644 --- a/test/CodeGen/R600/or.ll +++ b/test/CodeGen/R600/or.ll @@ -1,11 +1,11 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; EG-CHECK: @or_v2i32 +; EG-CHECK-LABEL: @or_v2i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @or_v2i32 +;SI-CHECK-LABEL: @or_v2i32 ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -18,13 +18,13 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) ret void } -; EG-CHECK: @or_v4i32 +; EG-CHECK-LABEL: @or_v4i32 ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @or_v4i32 +;SI-CHECK-LABEL: @or_v4i32 ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} ;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -38,3 +38,16 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +; EG-CHECK-LABEL: @or_i64 +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[3].X +; SI-CHECK-LABEL: @or_i64 +; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}} +; SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]}} +define void @or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = or i64 %a, %b + store i64 %0, i64 addrspace(1)* %out + ret void +} |