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-rw-r--r--test/CodeGen/MSP430/setcc.ll18
-rw-r--r--test/CodeGen/X86/xor.ll12
2 files changed, 20 insertions, 10 deletions
diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
index c99b17e143..05f9acd448 100644
--- a/test/CodeGen/MSP430/setcc.ll
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -32,10 +32,10 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
}
; CHECK:sccwne:
; CHECK: cmp.w r14, r15
-; CHECK: mov.w r2, r15
-; CHECK: rra.w r15
-; CHECK: and.w #1, r15
-; CHECK: xor.w #1, r15
+; CHECK: mov.w r2, r12
+; CHECK: rra.w r12
+; CHECK: mov.w #1, r15
+; CHECK: bic.w r12, r15
define i16 @sccweq(i16 %a, i16 %b) nounwind {
%t1 = icmp eq i16 %a, %b
@@ -55,9 +55,8 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
}
; CHECK:sccwugt:
; CHECK: cmp.w r15, r14
-; CHECK: mov.w r2, r15
-; CHECK: and.w #1, r15
-; CHECK: xor.w #1, r15
+; CHECK: mov.w #1, r15
+; CHECK: bic.w r2, r15
define i16 @sccwuge(i16 %a, i16 %b) nounwind {
%t1 = icmp uge i16 %a, %b
@@ -76,9 +75,8 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
}
; CHECK:sccwult:
; CHECK: cmp.w r14, r15
-; CHECK: mov.w r2, r15
-; CHECK: and.w #1, r15
-; CHECK: xor.w #1, r15
+; CHECK: mov.w #1, r15
+; CHECK: bic.w r2, r15
define i16 @sccwule(i16 %a, i16 %b) nounwind {
%t1 = icmp ule i16 %a, %b
diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index 996bfc40ee..2408bfe72c 100644
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -142,3 +142,15 @@ entry:
; X32: test8:
; X32: notl %eax
}
+
+define i32 @test9(i32 %a) nounwind {
+ %1 = and i32 %a, 4096
+ %2 = xor i32 %1, 4096
+ ret i32 %2
+; X64: test9:
+; X64: notl [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG:%[a-z]+]]
+; X32: test9:
+; X32: notl [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG:%[a-z]+]]
+}