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* [DAG] Refactor ReassociateOps - no functional change intended.Juergen Ributzka2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199146 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a check that the host compiler is modern to CMake, take 1. This isChandler Carruth2014-01-13
| | | | | | | | | | | | | likely to be reverted and re-applied a few times. The minimum versions we're aiming at: GCC 4.7 Clang 3.1 MSVC 17.0 (Visual Studio 2012) Let me know if something breaks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199145 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAG] Teach DAG to also reassociate vector operationsJuergen Ributzka2014-01-13
| | | | | | | | | | This commit teaches DAG to reassociate vector ops, which in turn enables constant folding of vector op chains that appear later on during custom lowering and DAG combine. Reviewed by Andrea Di Biagio git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199135 91177308-0d34-0410-b5e6-96231b3b80d8
* Hide the pre-RA-sched= option.Andrew Trick2014-01-13
| | | | | | | | | This is a very confusing option for a feature that will go away. -enable-misched is exposed instead to help triage issues with the new scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199133 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocksWeiming Zhao2014-01-13
| | | | | | | | | | The issue is caused when Post-RA scheduler reorders a bundle instruction (IT block). However, it only flips the CPSR liveness of the bundle instruction, leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes Thumb2SizeReduction.cpp::ReduceMBB(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
* Update getLazyBitcodeModule to use ErrorOr for error handling.Rafael Espindola2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199125 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix assertion failure caused by an invalid comparison between ↵Andrea Di Biagio2014-01-13
| | | | | | | | | | | | | | APInt values. APInt only knows how to compare values with the same BitWidth and asserts in all other cases. With this fix, function PerformORCombine does not use the APInt equality operator if the APInt values returned by 'isConstantSplat' differ in BitWidth. In that case they are different and no comparison is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix indentation.Joerg Sonnenberger2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199118 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Flesh out stackrestore test (frame-11.ll)Richard Sandiford2014-01-13
| | | | | | | ...so that it does something vaguely sensible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199117 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add "volatile" to a dead store in variable-loc.llRichard Sandiford2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199116 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve risbg-01.ll testRichard Sandiford2014-01-13
| | | | | | | | | | | | | | | The old mask in f24 wasn't well chosen because the lshr would always be zero. CodeGen didn't detect this but InstCombine would. The new mask ensures that both shifts are needed. f26 is specifically testing for a wrap-around mask. The AND can be applied to just the shift left, either before or after the shift. Again, CodeGen kept it in the original form but InstCombine would mask after the shift instead. The exact choice of NILF isn't important for the test so I just dropped it and kept the rotate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199115 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Optimize (sext (ashr (shl ...), ...))Richard Sandiford2014-01-13
| | | | | | | | | | | ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a -Wdocumentation warning.Chris Lattner2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199113 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add test for r199108. Oops.Tim Northover2014-01-13
| | | | | | rdar://problem/15800156 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199109 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.Tim Northover2014-01-13
| | | | | | | | | | | | Previously we only used GPR for the destination placeholder in "ldr rD, [pc, incorrect codegen under the integrated assembler. This should fix both issues (which probably only affect MachO targets at the moment). rdar://problem/15800156 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199108 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Fix retq/retl handling in 64-bit modeDavid Woodhouse2014-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | This finishes the job started in r198756, and creates separate opcodes for 64-bit vs. 32-bit versions of the rest of the RET instructions too. LRETL/LRETQ are interesting... I can't see any justification for their existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no need for a REX.W prefix for LRETQ. But this is what GAS does, and my Sandybridge CPU and an Opteron 6376 concur when tested as follows: asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:"); asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:"); asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to match it. I don't quite understand how the Intel syntax parsing for ret instructions is working, despite r154468 allegedly fixing it. Aren't the explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at least made the 'lretq' work with (and indeed *require*) the 'q'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Split DominatorTree into a concrete analysis result object whichChandler Carruth2014-01-13
| | | | | | | | | | | | | | | | | | | | | | | can be used by both the new pass manager and the old. This removes it from any of the virtual mess of the pass interfaces and lets it derive cleanly from the DominatorTreeBase<> template. In turn, tons of boilerplate interface can be nuked and it turns into a very straightforward extension of the base DominatorTree interface. The old analysis pass is now a simple wrapper. The names and style of this split should match the split between CallGraph and CallGraphWrapperPass. All of the users of DominatorTree have been updated to match using many of the same tricks as with CallGraph. The goal is that the common type remains the resulting DominatorTree rather than the pass. This will make subsequent work toward the new pass manager significantly easier. Also in numerous places things became cleaner because I switched from re-running the pass (!!! mid way through some other passes run!!!) to directly recomputing the domtree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199104 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM][cleanup] Clean up comments and use modern doxygen in this file.Chandler Carruth2014-01-13
| | | | | | | This is a precursor to breaking the pass that computes the DominatorTree apart from the concrete DominatorTree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199103 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-13
| | | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Fix the const-correctness of the generic DominatorTreeBase toChandler Carruth2014-01-13
| | | | | | | | | | | | | | | | | support notionally const queries even though they may trigger DFS numbering updates. The updating of DFS numbers and tracking of slow queries do not mutate the observable state of the domtree. They should be const to differentiate them from the APIs which mutate the tree directly to do incremental updates. This will make it possible in a world where the DominatorTree is not a pass but merely the result of running a pass to derive DominatorTree from the base class as it was originally designed, removing a huge duplication of API in DominatorTree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199101 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Pull the generic graph algorithms and data structures for dominatorChandler Carruth2014-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | trees into the Support library. These are all expressed in terms of the generic GraphTraits and CFG, with no reliance on any concrete IR types. Putting them in support clarifies that and makes the fact that the static analyzer in Clang uses them much more sane. When moving the Dominators.h file into the IR library I claimed that this was the right home for it but not something I planned to work on. Oops. So why am I doing this? It happens to be one step toward breaking the requirement that IR verification can only be performed from inside of a pass context, which completely blocks the implementation of verification for the new pass manager infrastructure. Fixing it will also allow removing the concept of the "preverify" step (WTF???) and allow the verifier to cleanly flag functions which fail verification in a way that precludes even computing dominance information. Currently, that results in a fatal error even when you ask the verifier to not fatally error. It's awesome like that. The yak shaving will continue... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199095 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "ReMat: fix overly cavalier attitude to sub-register indices"Tim Northover2014-01-13
| | | | | | | | | | Very sorry, this was a premature patch that I still need to investigate and finish off (for some reason beyond me at the moment it doesn't actually fix the issue in all cases). This reverts commit r199091. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199093 91177308-0d34-0410-b5e6-96231b3b80d8
* Docs: fix sign of division and increase equivocation on code generated.Tim Northover2014-01-13
| | | | | | I should have been a politician. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199092 91177308-0d34-0410-b5e6-96231b3b80d8
* ReMat: fix overly cavalier attitude to sub-register indicesTim Northover2014-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two attempted optimisations in reMaterializeTrivialDef, trying to avoid promoting the size of a register too much when rematerializing. Unfortunately, both appear to be flawed. First, we see if the original register would have worked, but this is inadequate. Consider: v1 = SOMETHING (v1 is QQ) v2:Q0 = COPY v1:Q1 (v1, v2 are QQ) ... uses of v2 In this case even though v2 *could* be used directly as the output of SOMETHING, this would set the wrong bits of the QQ register involved. The correct rematerialization must be: v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ) ... uses of v2:Q1_Q2 For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try to hunt for a class between v1 and v2 that works. Unfortunately, this is also wrong: v1 = SOMETHING (v1 is QQ) v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ) ... uses of v2 as a QQQ The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current logic would decide that v2 could be a QQ (no interest is taken in later uses). This patch, therefore, always accepts the widened register class without trying to be clever. Generally there is no penalty to this (e.g. in the common GR32 < GR64 case, expanding the width doesn't matter because it's not like you were going to do anything else with the high bits of a GR32 register). It can increase register pressure in cases like the ARM VFP regs though (multiple non-overlapping but equivalent subregisters). Hopefully this situation is rare enough that it won't matter. Unfortunately, no in-tree targets actually expose this as far as I can tell (there are so few isAsCheapAsAMove instructions for it to trigger on) so I've been unable to produce a test. It was exposed in our ARM64 SPEC tests though, and I will be adding a test there that we should be able to contribute soon(TM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199091 91177308-0d34-0410-b5e6-96231b3b80d8
* [cleanup] Re-sort the examples #include lines with my sort_includesChandler Carruth2014-01-13
| | | | | | script. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199089 91177308-0d34-0410-b5e6-96231b3b80d8
* [cleanup] Fix the includes in the examples for r199082.Chandler Carruth2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199087 91177308-0d34-0410-b5e6-96231b3b80d8
* [cleanup] Switch comments to use '\brief' style instead of '@brief'Chandler Carruth2014-01-13
| | | | | | | | style, and remove some unnecessary comments (the code is perfectly self-documenting here). Also clang-format the function declarations as they wrap cleanly now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199084 91177308-0d34-0410-b5e6-96231b3b80d8
* [cleanup] Move the Dominators.h and Verifier.h headers into the IRChandler Carruth2014-01-13
| | | | | | | | | | | | | | | | | | directory. These passes are already defined in the IR library, and it doesn't make any sense to have the headers in Analysis. Long term, I think there is going to be a much better way to divide these matters. The dominators code should be fully separated into the abstract graph algorithm and have that put in Support where it becomes obvious that evn Clang's CFGBlock's can use it. Then the verifier can manually construct dominance information from the Support-driven interface while the Analysis library can provide a pass which both caches, reconstructs, and supports a nice update API. But those are very long term, and so I don't want to leave the really confusing structure until that day arrives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199082 91177308-0d34-0410-b5e6-96231b3b80d8
* [cleanup] Add a missing include exposed by resorting other includes.Chandler Carruth2014-01-13
| | | | | | Should fix the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199081 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-sort #include lines again, prior to moving headers around.Chandler Carruth2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199080 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Wire up support for writing bitcode with new PM.Chandler Carruth2014-01-13
| | | | | | | | | | This moves the old pass creation functionality to its own header and updates the callers of that routine. Then it adds a new PM supporting bitcode writer to the header file, and wires that up in the opt tool. A test is added that round-trips code into bitcode and back out using the new pass manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199078 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Put together rm(1) and ↵NAKAMURA Takumi2014-01-13
| | | | | | mkdir(1) at the top. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199077 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] Move BUG_REPORT_URL from clang to llvm.NAKAMURA Takumi2014-01-13
| | | | | | | | | | It was too late to set BUG_REPORT_URL after configure_file(config.h). BUG_REPORT_URL in config.h.cmake would be updated at 2nd run of cmake. It caused many recompilations. FYI, configure handles BUG_REPORT_URL in llvm side. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199076 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Wire up support for printing assembly output from the opt command.Chandler Carruth2014-01-13
| | | | | | This lets us round-trip IR in the expected manner with the opt tool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199075 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Add an enum for describing the desired output strategy, and runChandler Carruth2014-01-13
| | | | | | | | that through the interface rather than a simple bool. This should allow starting to wire up real output to round-trip IR through opt with the new pass manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199071 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Add missing patterns for bitcast from or to v1f64Kevin Qin2014-01-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199070 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Add more scenarios to use perm instructions when lowering ↵Kevin Qin2014-01-13
| | | | | | | | | | | | | | | | shuffle_vector This patch covered 2 more scenarios: 1. Two operands of shuffle_vector are the same, like %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 2. One of operands is undef, like %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> After this patch, perm instructions will have chance to be emitted instead of lots of INS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199069 91177308-0d34-0410-b5e6-96231b3b80d8
* correct target directive handling error handlingSaleem Abdulrasool2014-01-13
| | | | | | | | | | | | | | The target specific parser should return `false' if the target AsmParser handles the directive, and `true' if the generic parser should handle the directive. Many of the target specific directive handlers would `return Error' which does not follow these semantics. This change simply changes the target specific routines to conform to the semantis of the ParseDirective correctly. Conformance to the semantics improves diagnostics emitted for the invalid directives. X86 is taken as a sample to ensure that multiple diagnostics are not presented for a single error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199068 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle bundled terminators in isBlockOnlyReachableByFallthrough.Jakob Stoklund Olesen2014-01-12
| | | | | | | | | | Targets like SPARC and MIPS have delay slots and normally bundle the delay slot instruction with the corresponding terminator. Teach isBlockOnlyReachableByFallthrough to find any MBB operands on bundled terminators so SPARC doesn't need to specialize this function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199061 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] Add a comment to tablegen's copy_if_different. Ninja reports every ↵NAKAMURA Takumi2014-01-12
| | | | | | action by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199058 91177308-0d34-0410-b5e6-96231b3b80d8
* raw_fd_ostream: Don't change STDERR to O_BINARY, or w*printf() (in assert()) ↵NAKAMURA Takumi2014-01-12
| | | | | | would barf wide chars after llvm::errs(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199057 91177308-0d34-0410-b5e6-96231b3b80d8
* Make test independent of schedulingNico Rieck2014-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199055 91177308-0d34-0410-b5e6-96231b3b80d8
* raw_stream formatter: [Win32] Use std::signbit() if available, instead of ↵NAKAMURA Takumi2014-01-12
| | | | | | | | _fpclass(). FIXME: It should be generic to C++11. For now, it is dedicated to mingw-w64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199052 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/shl_undef.ll: Tweak to satisfy r199050.NAKAMURA Takumi2014-01-12
| | | | | | Use intel syntax, or "shl" might hit "pushl". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199051 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix non-deterministic SDNodeOrder-dependent codegenNico Rieck2014-01-12
| | | | | | | Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199050 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Add module and function printing passes for the new pass manager.Chandler Carruth2014-01-12
| | | | | | | | | This implements the legacy passes in terms of the new ones. It adds basic testing using explicit runs of the passes. Next up will be wiring the basic output mechanism of opt up when the new pass manager is engaged unless bitcode writing is requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199049 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Revert an accidental commit of total BS code. This was halfwayChandler Carruth2014-01-12
| | | | | | | through being editted, and I forgot to delete it before committing. What's more awesome is that it compiles cleanly! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199048 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Simplify the IR printing passes significantly now that a narrowerChandler Carruth2014-01-12
| | | | | | | | | | API is exposed. This removes the support for deleting the ostream, switches the member and constructor order arround to be consistent with the creation routines, and switches to using references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199047 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Update one user of the printing pass API that I missed.Chandler Carruth2014-01-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199046 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Simplify the interface exposed for IR printing passes.Chandler Carruth2014-01-12
| | | | | | | | | | | | Nothing was using the ability of the pass to delete the raw_ostream it printed to, and nothing was trying to pass it a pointer to the raw_ostream. Also, the function variant had a different order of arguments from all of the others which was just really confusing. Now the interface accepts a reference, doesn't offer to delete it, and uses a consistent order. The implementation of the printing passes haven't been updated with this simplification, this is just the API switch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199044 91177308-0d34-0410-b5e6-96231b3b80d8
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