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* Temporarily revert this to bring back the bots.Eric Christopher2012-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162722 91177308-0d34-0410-b5e6-96231b3b80d8
* More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen2012-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-27
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
* Add --program-prefix support to build.Sebastian Pop2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162707 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix compile error when building with C++11 - clang thinks that PRIx64 is a ↵Marshall Clow2012-08-27
| | | | | | user-defined suffix or something git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162704 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-27
| | | | | | | <rdar://problem/12183003> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use for loops for code that is only intended to execute once. NoDan Gohman2012-08-27
| | | | | | | intended functionality change. Thanks to Ahmed Charles for spotting it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162686 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Rafael Espindola2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162678 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment for function RuntimeDyldImpl.resolveRelocation()Danil Malyshev2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162677 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the the block_node_iterator of Region, replace it by the block_iterator.Hongbin Zheng2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162672 91177308-0d34-0410-b5e6-96231b3b80d8
* Support MIPS DSP Rev2 intrinsics.Simon Atanasyan2012-08-27
| | | | | | | The patch reviewed by Akira Hatanaka. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162668 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on ↵NAKAMURA Takumi2012-08-27
| | | | | | non-x86 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162667 91177308-0d34-0410-b5e6-96231b3b80d8
* DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.NAKAMURA Takumi2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162665 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was ↵NAKAMURA Takumi2012-08-27
| | | | | | incompatible on i686 and Windows x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162664 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper2012-08-27
| | | | | | SelectionDAGBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
* Commit test change for r162658.Craig Topper2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162660 91177308-0d34-0410-b5e6-96231b3b80d8
* [DebugInfo] fixup for r162657: update CMakeLists.txtAlexey Samsonov2012-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162659 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper2012-08-27
| | | | | | unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658 91177308-0d34-0410-b5e6-96231b3b80d8
* Add basic support for .debug_ranges section to LLVM's DebugInfo library.Alexey Samsonov2012-08-27
| | | | | | | | | | | | This section (introduced in DWARF-3) is used to define instruction address ranges for functions that are not contiguous and can't be described by low_pc/high_pc attributes (this is the usual case for inlined subroutines). The patch is the first step to support fetching complete inlining info from DWARF. Reviewed by Benjamin Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162657 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper2012-08-27
| | | | | | removing the need for an explicit 'neverHasSideEffects = 1' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
* FMA3 tests on bdver2 target for changes made in rev 162012. Also madeAnitha Boyapati2012-08-27
| | | | | | | | | corresponding changes to existing tests for darwin triple to ensure that same pattern is tested for bdver2 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162655 91177308-0d34-0410-b5e6-96231b3b80d8
* Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper2012-08-27
| | | | | | instruction and an AVX2 instruction rather than relying on AddedComplexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure that FMA3 is favored even when FMA4 is also enabled. Test case for ↵Craig Topper2012-08-27
| | | | | | r162454. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162653 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass -lLTO after gold-plugin.o so that it gets used in systems that default toRafael Espindola2012-08-27
| | | | | | | --as-needed. Patch by Felix Geyer. Fixes pr13262. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162652 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ↵Craig Topper2012-08-26
| | | | | | ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-24
| | | | | | | Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
* Missed tLEApcrelJT.Jakob Stoklund Olesen2012-08-24
| | | | | | | ARMConstantIslandPass expects this instruction to stay in the same basic block as the jump table branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615 91177308-0d34-0410-b5e6-96231b3b80d8
* Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | | | | | | | | | | | | | Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | | It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop inferring isVariadic from instruction patterns.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | | | | | | | | | | Instructions are now only marked as variadic if they use variable_ops in their ins list. A variadic SDNode is typically used for call nodes that have the call arguments as operands. A variadic MachineInstr can actually encode a variable number of operands, for example ARM's stm/ldm instructions. A call instruction does not have to be variadic. The call argument registers are added as implicit operands. This change remove the MCID::Variadic flags from most call and return instructions, allowing us to better verify their operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | The ARM BL and BLX instructions don't have predicate operands, but the thumb variants tBL and tBLX do. The argument registers should be added as implicit uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen2012-08-24
| | | | | | | There is special magic happening when returning floating point values on the x87 stack. The RET instructions get extra f80 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen2012-08-24
| | | | | | | It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162591 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka2012-08-24
| | | | | | | | second operand is MipsISD::GPRel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot to check in ProfileDataTypes.h in r162576Manman Ren2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162578 91177308-0d34-0410-b5e6-96231b3b80d8
* Profile: move a single enum out of ProfileInfoTypes.h into a new Manman Ren2012-08-24
| | | | | | | | | | | | | ProfileDataTypes.h header. With this patch the old and new profiling code can exist side-by-side. The new profiling code will be submitted soon and it only supports insert-edge-profiling for now and will not depend on ProfileInfo. Patch by Alastair Murray. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162576 91177308-0d34-0410-b5e6-96231b3b80d8
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-24
| | | | | | | | | | | | | | | | the case of multiple edges from one block to another. A simple example is a switch statement with multiple values to the same destination. The definition of an edge is modified from a pair of blocks to a pair of PredBlock and an index into the successors. Also set the weight correctly when building SelectionDAG from LLVM IR, especially when converting a Switch. IntegersSubsetMapping is updated to calculate the weight for each cluster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162572 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify explicit instruction properties when they can be inferred.Jakob Stoklund Olesen2012-08-24
| | | | | | | | | It is now allowed to explicitly set hasSideEffects, mayStore, and mayLoad on instructions with patterns. Verify that the patterns are consistent with the explicit flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162569 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan/tsan] rename FunctionBlackList* to BlackList* as this class is not ↵Kostya Serebryany2012-08-24
| | | | | | limited to functions any more git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162566 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan/tsan] extend the functionality of FunctionBlackList to globals and ↵Kostya Serebryany2012-08-24
| | | | | | modules. Patch by Reid Watson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162565 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-24
| | | | | | | In collaboration with Adhemerval Zanella. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
* GVN: Fix quadratic runtime on the number of switch cases.Benjamin Kramer2012-08-24
| | | | | | | | No intended behavior change. This was introduced in r162023. With the fixed algorithm a Release build of ARMInstPrinter.cpp goes from 16s to 10s on a 2011 MBP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162559 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix load/store SDNode flags.Jakob Stoklund Olesen2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162558 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing SDNPSideEffect flags.Jakob Stoklund Olesen2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more mayLoad workarounds.Jakob Stoklund Olesen2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162556 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to appease MSVC even more elaborately in the alignment hacking space.Chandler Carruth2012-08-24
| | | | | | | | | | | | | | | | | | | | MSVC doesn't support passing by-value parameters with alignment of 16-bytes or higher apparantly. What is deeply confusing is that it seems to *sometimes* (but not always) apply this to any type whose alignment is set using __declspec(align(...)). This caused lots of errors when we switch SmallVector over to use the automatically aligned character array utilities as they used __declspec(align(...)) heavily. As a pretty horrible but effective work-around, we instead cherry pick the smallest alignment sizes with specific types that happen to have the correct alignment, and then fall back to the attribute solution past them. This should resolve the MSVC build errors folks have been hitting. Sorry for that. In good news, it will do this without introducing other UB I hope. =] Thanks to Timur Iskhodzhanov for helping me test this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162549 91177308-0d34-0410-b5e6-96231b3b80d8
* Custom lower FMA intrinsics to target specific nodes and remove the patterns.Craig Topper2012-08-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
* Use DW_FORM_flag_present to save space in debug information if we'reEric Christopher2012-08-24
| | | | | | | | not in darwin gdb compat mode. Fixes rdar://10975088 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162526 91177308-0d34-0410-b5e6-96231b3b80d8
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